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#1 opened Aug 18, 2020 by eine
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Issues list

NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL cat: Cores Cores, designs, (co-simulation) libraries, etc.
#36 opened Feb 5, 2022 by umarcor
OSVVM & UVVM: Differences and Unification cat: Articles Articles, reports, books...
#33 opened Oct 30, 2021 by umarcor
Mixed HDL on Fomu, with GHDL and Yosys cat: Articles Articles, reports, books...
#26 opened Dec 2, 2020 by umarcor
VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect cat: Cores Cores, designs, (co-simulation) libraries, etc.
#24 opened Nov 30, 2020 by tmeissner
VHDL needs you! cat: News News
#22 opened Nov 13, 2020 by umarcor
SusanaCanel - Proyectos VHDL cat: Articles Articles, reports, books...
#15 opened Sep 18, 2020 by umarcor
Open Source Formal Verification in VHDL cat: Articles Articles, reports, books...
#13 opened Sep 7, 2020 by Ahmad-Zaklouta
Learning FPGA programming, key points for a software developer cat: Articles Articles, reports, books...
#10 opened Sep 1, 2020 by eine
What’s new in VHDL-2019 - VHDLwhiz cat: Articles Articles, reports, books...
#9 opened Aug 28, 2020 by tmeissner
Create your own VVC for UVVM cat: Articles Articles, reports, books...
#7 opened Aug 19, 2020 by Ahmad-Zaklouta
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