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NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL
cat: CoresCores, designs, (co-simulation) libraries, etc.Cores, designs, (co-simulation) libraries, etc.Status: Open.#36 In VHDL/news;- Status: Open.#35 In VHDL/news;
OSVVM & UVVM: Differences and Unification
cat: ArticlesArticles, reports, books...Articles, reports, books...Status: Open.#33 In VHDL/news;- Status: Open.#32 In VHDL/news;
Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry
cat: ArticlesArticles, reports, books...Articles, reports, books...Status: Open.#31 In VHDL/news;- Status: Open.#30 In VHDL/news;
- Status: Open.#27 In VHDL/news;
Mixed HDL on Fomu, with GHDL and Yosys
cat: ArticlesArticles, reports, books...Articles, reports, books...Status: Open.#26 In VHDL/news;VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect
cat: CoresCores, designs, (co-simulation) libraries, etc.Cores, designs, (co-simulation) libraries, etc.Status: Open.#24 In VHDL/news;- Status: Open.#23 In VHDL/news;
- Status: Open.#22 In VHDL/news;
Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools
cat: CoresCores, designs, (co-simulation) libraries, etc.Cores, designs, (co-simulation) libraries, etc.cat: ToolsToolsToolsStatus: Open.#21 In VHDL/news;