fix dependency for vhdl instances inside (Sysytem) verilog modules #979
+238
−5
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
_find_verilog_module_dependencies scans for vhdl primary units
Parse interfaces as modules
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
I have found that vunit don't build full dependency between verilog and vhdl #929.
I have updated project.py to also check if a instance is a VHDL-instance. I have also updated verilog/parser.py to parse interfaces as modules (which they basically are).
tox -e py38-unit,py38-acceptance-modelsim
passes (questa 2023.4) with the exception of tb_uart_lib.tb_uart_rx.test_receives_one_byte (due to #889)