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fix dependency for vhdl instances inside (Sysytem) verilog modules #979

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Commits on Nov 21, 2023

  1. Update project.py

    _find_verilog_module_dependencies scans for vhdl primary units
    roynil committed Nov 21, 2023
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  2. Update parser.py

    Parse interfaces as modules
    roynil committed Nov 21, 2023
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Commits on Nov 24, 2023

  1. Mixed (sv top-level TB) examples

    Ronny Nilsson committed Nov 24, 2023
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  2. added add_vhdl_builtins()

    Ronny Nilsson committed Nov 24, 2023
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  3. Added examples/mixed tests

    Ronny Nilsson committed Nov 24, 2023
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Commits on Nov 27, 2023

  1. updated after reformat

    Ronny Nilsson committed Nov 27, 2023
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