Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

fix dependency for vhdl instances inside (Sysytem) verilog modules #979

Open
wants to merge 6 commits into
base: master
Choose a base branch
from

Commits on Nov 21, 2023

  1. Update project.py

    _find_verilog_module_dependencies scans for vhdl primary units
    roynil authored Nov 21, 2023
    Configuration menu
    Copy the full SHA
    cbe3048 View commit details
    Browse the repository at this point in the history
  2. Update parser.py

    Parse interfaces as modules
    roynil authored Nov 21, 2023
    Configuration menu
    Copy the full SHA
    6bf6148 View commit details
    Browse the repository at this point in the history

Commits on Nov 24, 2023

  1. Mixed (sv top-level TB) examples

    Ronny Nilsson committed Nov 24, 2023
    Configuration menu
    Copy the full SHA
    71bfee7 View commit details
    Browse the repository at this point in the history
  2. added add_vhdl_builtins()

    Ronny Nilsson committed Nov 24, 2023
    Configuration menu
    Copy the full SHA
    153d400 View commit details
    Browse the repository at this point in the history
  3. Added examples/mixed tests

    Ronny Nilsson committed Nov 24, 2023
    Configuration menu
    Copy the full SHA
    739787f View commit details
    Browse the repository at this point in the history

Commits on Nov 27, 2023

  1. updated after reformat

    Ronny Nilsson committed Nov 27, 2023
    Configuration menu
    Copy the full SHA
    9ea20e5 View commit details
    Browse the repository at this point in the history