Python's IL bindings reported no operands for ASSERT and FORCE_VER, and the
wrong variables as read or written for a handful of MLIL ops. ILOperations
named some operands after their slots rather than their properties. LLIL
also turned negative register-stack adjustments into -1, HLIL's ROR read a
carry it doesn't have, and a few HLIL builders stored their operands in the
wrong slots.

Now each op reports its operands and variables correctly, and the builders
store their operands in the right slots.