Intel Stratix10/Agilex SOCFPGA Board Support Package

1. About this document
======================

This document describes common and non-hardware specific information.
Please refer to README.hardware for hardware specific information.

Dependencies
------------
This layer depends on the oe-core version supplied with Wind River Linux
and the wrlinux layer.

Maintenance
-----------
This layer is maintained by Wind River Systems, Inc.
Contact <support@windriver.com> or your support representative for more
information on submitting changes.

Building the intel-socfpga layer
--------------------------------
This layer should be added to bblayers.conf. This is done automatically
when using the Wind River setup.sh wrapper.

License
-------
Copyright (C) 2025 Wind River Systems, Inc.

Source code included in the tree for individual recipes is under the LICENSE
stated in the associated recipe (.bb file) unless otherwise stated.

The metadata is under the following license unless otherwise stated.

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

2. BSP Kernel and Distros
=========================

The following table summarizes the valid Wind River Linux distros for this BSP.
'Y' in each content cell stands for supported; 'N' stands for not supported:

  +--------------+-------------+------------------+-------------------+--------------+
  | valid/distro |   wrlinux   | wrlinux-graphics | wrlinux-installer | wrlinux-tiny |
  +--------------+-------------+------------------+-------------------+--------------+
  |    valid     |      Y      |        N         |         N         |       N      |
  +--------------+-------------+------------------+-------------------+--------------+

For the supported kernel type for this BSP, please check the TARGET_SUPPORTED_KTYPES
by running 'bitbake -e virtual/kernel | grep "^TARGET_SUPPORTED_KTYPES="'.

Note: The preempt-rt kernel type can be used with this BSP/Machine.

3. Board Specific Patches
=========================

To get a list of patches applied to the kernel specific to this BSP,
along with patch descriptions, use git to see what changed on the default
kernel (git whatchanged <kernel_type>..<bsp_name>). For example:

  # cd tmp/work-shared/<bsp_name>/kernel-source
  # git whatchanged v6.12/standard/base..v6.12/standard/intel-socfpga


4. Boot Instructions
====================

The DTB file can be built automatically or you can generate it manually in a
single step.

To generate the DTB manually, change into build directory, then run the
following:

  # bitbake -c devshell linux-yocto
  For Stratix10 platform
  # make altera/socfpga_stratix10_socdk.dtb
  For Agilex platform
  # make intel/socfpga_agilex_socdk.dtb

The DTB can then be found in the

linux-<bsp_name>-<kernel type>-build/arch/arm64/boot/dts/altera
linux-<bsp_name>-<kernel type>-build/arch/arm64/boot/dts/intel

directory.

4.1 NFS Root File System
------------------------

Configure u-boot with target IP, tftp server, netmask and other required
network values in advance, and then run below commands.

For Stratix10 platform:
SOCFPGA_STRATIX10 # run fatscript
SOCFPGA_STRATIX10 # tftp 0x2000000 "/<tftp root>/Image"
SOCFPGA_STRATIX10 # tftp 0x8000000 "/<tftp root>/socfpga_stratix10_socdk.dtb"
SOCFPGA_STRATIX10 # run linux_qspi_enable
SOCFPGA_STRATIX10 # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
			  nfsroot=<nfs server>:<nfs root>,nolock \
			  ip=<target IP>::<gateway>:<netmask>::eth0:off
SOCFPGA_STRATIX10 # booti 0x2000000 - 0x8000000

For Agilex platform:
Boot from SD card
SOCFPGA_AGILEX # run fatscript
Boot from NAND flash
SOCFPGA_AGILEX # run fpgaload

SOCFPGA_AGILEX # tftp 0x2000000 "/<tftp root>/Image"

Boot from SD card
SOCFPGA_AGILEX # tftp 0x8000000 "/<tftp root>/socfpga_agilex_socdk.dtb"
Boot from NAND flash
SOCFPGA_AGILEX # tftp 0x8000000 "/<tftp root>/socfpga_agilex_socdk_nand.dtb"

SOCFPGA_AGILEX # run linux_qspi_enable
SOCFPGA_AGILEX # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
			  nfsroot=<nfs server>:<nfs root>,nolock \
			  ip=<target IP>::<gateway>:<netmask>::eth0:off
SOCFPGA_AGILEX # booti 0x2000000 - 0x8000000

4.2 Rootfs on MMC/SD
--------------------

An ext3/ext4 filesystem can be created on the MMC/SD using standard
techniques.

4.2.1 Deployment
----------------

After loading the kernel, pass kernel arguments like following:

    root=/dev/mmcblk0p2 rw console=ttyS0,115200n8 rootwait

4.3 RAM Root File System
------------------------

4.3.1 Create initramfs image
----------------------------

Add below content in <project-path>/conf/local.conf.

	INITRAMFS_FSTYPES += "cpio.gz.u-boot"

Build the gzipped initramfs image with below command.

	# bitbake wrlinux-image-initramfs

The initramfs image is generated in <project-path>/build/tmp/deploy/images/intel-socfpga-64.

4.3.2 Deployment
----------------

After the BootLoader bootup, load initramfs, kernel and DTB:

	For Stratix10 platform
	# tftp 0x8000000 /<tftp root>/socfpga_stratix10_socdk.dtb
	For Agilex platform
	# tftp 0x8000000 /<tftp root>/socfpga_agilex_socdk.dtb
	# tftp 0x2000000 /<tftp root>/Image
	# tftp 0x5000000 wrlinux-image-initramfs-intel-socfpga-64.cpio.gz.u-boot

then you need to set initrd_high to restrict positioning of initrd ramdisk images:

	# setenv initrd_high 0x8000000

and then you need to pass the kernel arguments as follows:

	# setenv bootargs 'root=/dev/ram0 rw ramdisk_size=0x6400'

Boot kernel with the following command:

	# booti 0x2000000 0x5000000 0x8000000


5. Features Notes
=================

5.1 LWH2F Bridge
----------------
The pre-built SD Image allows you to test out the Lightweight HPS-to-FPGA (LWH2F) bridge on the Stratix10/Agilex SoC.
This bridge connects the Hard Processor System (HPS) to the FPGA core logic and can control FPGA IPs such as FPGA
LEDs and switches.

5.1.1 Known issue
-----------------
Stratix10/Agilex SOCFPGA doesn't support for controlling fpga bridge from linux kernel.
We can enable/disable fpga bridge in bootloader with command "bridge enable/disable"

5.2 HPS IO
----------
There are 3 LEDs on HPS IO48 OOBE Card that is a daughter card.
Run below command to turn on/off the 3 LEDs.
- To turn on/off HPS_LED1(D6):
root@intel-socfpga-64:~# echo 1 > /sys/class/leds/hps_led0/brightness
root@intel-socfpga-64:~# echo 0 > /sys/class/leds/hps_led0/brightness

- To turn on/off HPS_LED2(D8):
root@intel-socfpga-64:~# echo 1 > /sys/class/leds/hps_led1/brightness
root@intel-socfpga-64:~# echo 0 > /sys/class/leds/hps_led1/brightness

- To turn on/off HPS_LED3(D7):
root@intel-socfpga-64:~# echo 1 > /sys/class/leds/hps_led2/brightness
root@intel-socfpga-64:~# echo 0 > /sys/class/leds/hps_led2/brightness


6. Creating Partitioned Images(WIC)
===================================

You can use the OpenEmbedded Image Creator, wic, to create a properly
partitioned image on an SD card. The wic command generates partitioned images
from existing OpenEmbedded build artifacts.
For more information about WIC, see:

https://docs.yoctoproject.org/singleindex.html#creating-partitioned-images-using-wic

This BSP supports SD card disk images.
After building the project, you will have a WIC image under the directory
tmp/deploy/images/<bsp name>/, for example:

For Stratix10 platform
tmp/deploy/images/intel-socfpga-64/wrlinux-image-std-intel-socfpga-64.rootfs-stratix10-socdk-mmc.wic

For Agilex platform
tmp/deploy/images/intel-socfpga-64/wrlinux-image-std-intel-socfpga-64.rootfs-agilex-socdk-mmc.wic

You can then write the output image to an SD card.

6.1 Burn images to SD card
--------------------------

To burn u-boot and WIC images to an SD card, you need to execute below command:

For Stratix10 platform
# dd if=wrlinux-image-std-intel-socfpga-64.rootfs-stratix10-socdk-mmc.wic of=/dev/your_sd_dev

For Agilex platform
# dd if=wrlinux-image-std-intel-socfpga-64.rootfs-agilex-socdk-mmc.wic of=/dev/your_sd_dev

6.2 Boot up wic image
---------------------

Power on board, system boots up automatically from SD card.

Note:
There are 2 kinds of bootloader in the boot partition, u-boot.img and u-boot.itb.
u-boot.img: It is created only based on u-boot code.
u-boot.itb: It is created by combining u-boot with atf.
Use different bootloader, it is need to merge separate u-boot-spl-dtb.hex file into
FPGA image *.sof file. Detailed steps, please refer to below link:
https://www.intel.com/content/www/us/en/docs/programmable/683847/21-4/creating-configuration-files-from-command-94890.html
https://www.intel.com/content/www/us/en/docs/programmable/683389/21-4/creating-configuration-files-from-command-94890.html

7. Tickless Feature
===================
When Tickless Feature is required, please add it by template in setup command line
	--templates=feature/full_nohz


8. Update FPGA configuration file
=================================
8.1 On the target, copy FPGA configuration file(*.rbf) to rootfs/lib/firmware,
    and make sure the name of *.rbf file is soc_<s10/agilex>_fpga_config.rbf.
	For Stratix10 platform
	# cp xxx/ghrd.core.rbf /lib/firmware/soc_s10_fpga_config.rbf
	# cp xxx/socfpga_stratix10_fpga_update.dtb /lib/firmware/
	For Agilex platform
	# cp xxx/ghrd.core.rbf /lib/firmware/soc_agilex_fpga_config.rbf
	# cp xxx/socfpga_agilex_fpga_update.dtb /lib/firmware/

8.2 On the target, apply the overlay
	# mkdir /sys/kernel/config/device-tree/overlays/0
	# cd /lib/firmware/
	For Stratix10 platform
	# echo socfpga_stratix10_fpga_update.dtb > /sys/kernel/config/device-tree/overlays/0/path
	For Agilex platform
	# echo socfpga_agilex_fpga_update.dtb > /sys/kernel/config/device-tree/overlays/0/path

8.3 On the target, if you want to do programming again, delete the overlay first before doing step 8.2.
	# rmdir /sys/kernel/config/device-tree/overlays/0

Note1:
User can download the pre-build FPGA image or FPGA project from below link:
https://releases.rocketboards.org/release/2021.11/.
About how to build FPGA project and generate ghrd.core.rbf file, please refer to below link:
https://rocketboards.org/foswiki/Documentation/Stratix10SoCGSRD

Note2:
If there is any device running on FPGA side, please stop it firstly.

Note3:
For Agilex platform, we need disable fcs in u-boot to avoid fcs secure policy
block writing images to FPGA Manager:
	# fdt addr ${fdt_addr};fdt resize;fdt set /soc/firmware/svc/fcs status disabled;

9. Remote System Update
=======================

Please follow below steps to run remote system update feature

9.1 Install necessary tool
--------------------------
Please download below 2 tools from https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html, linux version.
- Quartus Prime Pro Edition Programmer and Tools v21.3
- Quartus Prime Pro Edition Software v21.3
Note: Please apply for license for building Stratix10/Agilex *.sof file.
      Customer also can get the pre-build *.sof file from https://releases.rocketboards.org/release/2021.11/.

9.2 Setting up the build environment
------------------------------------
Start an embedded command shell
	# ~/intelFPGA_pro/20.4/embedded/embedded_command_shell.sh
Create the top folder used to store all the example files
	# rm -rf  ~/rsu_example
	# cd ~/rsu_example

9.3 Building hardware project
-----------------------------
Create a few images for testing: 0-factory, 1-production1, 2-production2, 3-production3
	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# cd ~/rsu_example
	# rm -rf hardware_designs
	# mkdir hardware_designs
	# git clone https://github.com/altera-opensource/ghrd-socfpga.git
	# cd ghrd-socfpga
	# git checkout -b QPDS-21.3pro-21.1std QPDS-21.3pro-21.1std

	For Stratix10 platform
	# cp -r s10_soc_devkit_ghrd ../hardware_designs
	# cd ../hardware_designs/s10_soc_devkit_ghrd

	For Agilex platform
	# cp -r agilex_soc_devkit_ghrd ../hardware_designs
	# cd ../hardware_designs/agilex_soc_devkit_ghrd

	# make clean && make scrub_clean && rm -rf output_files
	# export IP_ROOTDIR=<path-to-quartus>/intelFPGA_pro/21.3/ip
	# make generate_from_tcl
	# make sof
	# cd ..

After building, there will be the following SOF files:
For Stratix10 platform
s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof
For Agilex platform
s10_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof

Note: For Agilex platform, set HPS_ENABLE_SGMII as 0 in below 2 files, because the sgmii feature needs special license on Agilex platform.
      agilex_soc_devkit_ghrd/Makefile
      agilex_soc_devkit_ghrd/board/board_devkit_make_config.inc

9.4 Building u-boot
-------------------

u-boot files for the 2 platforms(Stratix10&Agilex) are also built when building intel-socfpga BSP project, they will be in below directories.
For Stratix10 platform
<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_stratix10_mmc_defconfig
For Agilex platform
<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_agilex_mmc_defconfig
<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_agilex_nand_defconfig

9.5 Add FSBL to the SOF file
----------------------------
The SOF files generated by the Quartus tool only contain the FPGA fabric configuration,
and we need to add the FSBL to them with the following commands:
# cd ~/rsu_example
# rm -rf sof_files
# mkdir sof_files
For Stratix10 platform
# for version in {0..3}
  do
	quartus_pfg -c -o hps_path=<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_stratix10_mmc_defconfig/u-boot-spl-dtb.hex \
	hardware_designs/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof sof_files/ghrd_hps.$version.sof
  done
For Agilex platform
# for version in {0..3}
  do
	quartus_pfg -c -o hps_path=<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_agilex_mmc_defconfig/u-boot-spl-dtb.hex \
	hardware_designs/s10_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof sof_files/ghrd_hps.$version.sof
  done

After building, there will be the following files generated:
~/rsu_example/sof_files/ghrd_hps.0.sof
~/rsu_example/sof_files/ghrd_hps.1.sof
~/rsu_example/sof_files/ghrd_hps.2.sof
~/rsu_example/sof_files/ghrd_hps.3.sof

9.6 Creating the Initial Flash Image
------------------------------------
1) Go to the folder ~/ and create a file named quartus.ini containing the following two lines:
PGM_ALLOW_MT25Q=ON
PGM_ALLOW_MX66U=ON
The above file will allow the Quartus tools to use the Micron MT25Q and Macronix MX66U devices.

2) Start the Quartus Programmer tool by running the "quartus_pgmw" command.
	# quartus_pgmw

3) Click File > Programming File Generator .. to start the Programming File Generator Tool.

4) Select the Device family to be Stratix 10/Agilex, and Configuration mode to be Active Serial x4.

5) Select the output file type as JIC, which is the format used by the Quartus Flash Programmer tool.
   Select the optiona .map and .rpd files to be generated. The .map file contains information
   about the flash layout. The .rpd file contains the full binary content of the flash, and is intended
   for external programmers. Change the Name to "initial_image".

6) Once the output type was selected, click on the Input Files tab.

7) In the Input Files tab click on Add Bitstream button, then browse to ~/rsu_example/sof_files/, select
   the file ghrd_hps.0.sof and click Open, ghrd_hps.0.sof is used to be the factory image. Do the same for
   the ghrd_hps.1.sof that is used to be initial production image.

8) After input file was added in the Input Files tab, click the Configuration Device tab.
   In the Configuration Device tab, click on Add Device, select the MT25QU02G in the pop-up window,
   then click OK. Once that is done, the window will show the default initial partitioning for RSU.

9) Select the FACTORY_IMAGE entry, and click the Edit… button. The Edit Partition window pops up.
   Select the Input file to be Bitstream_1 (ghrd_hps.0.sof). Change Address Mode to Block, because
   it is need to make sure that leave enough space for the biggest anticipated factory image.
   Set the End Address to 0x0090FFFF in order to reserve 8MB for the factory image. This end address
   was calculated by adding 16MB to the end of the BOOT_INFO partition. Click OK.

10) Select the MT25QU02G flash device in the Configuration Device tab by clicking it, then click the
    Add Partition button to open the Add Partition window. Leave the Name as P1 and select the Input
    file as Bitstream_2(ghrd_hps_1.sof). This will be the initial production image. Select the Page to
    be 1. It means it P1(initial production image) has the highest priority of all production images.
    Select the Address Mode as Block and allocate 16MB of data by setting Start Address = 0x01000000
    and End Address = 0x01FFFFFF.

11) Create another two partitions P2 and P3 using the same procedure as for the previous step, but set
    the Input file to None, leave Page unchanged (it does not matter for empty partitions).
    Select the Address Mode as Block and set the start and end addresses as follows:
	P2: Start Address = 0x02000000 and End Address = 0x02FFFFFF.
	P3: Start Address = 0x03000000 and End Address = 0x03FFFFFF.

12) Click Select … to select the Flash loader. The flash loader will become part of the JIC file and will
    be used by the Flash Programmer tool. Select the desired Device family and Device name as below:
	Device family: Stratix 10/Agilex
	Device name: 1SX280LU3/AGFB014R24B

13) Click on Generate button to generate the initial flash image as ~/rsu_example/initial_image.jic and
    the map file as ~/rsu_example/initial_image_jic.map.

14). Click on File > Save As .. and save the file as ~/rsu_example/initial_image.pfg. This file would be
     useful later, if it is need to re-generate the initial image, only one below command can generate it.
	# quartus_pfg -c initial_image.pfg

9.7 Create Remote Update Production Image
-----------------------------------------
The RSU Production Images is able to be created from the Programming File Generator GUI tool, but the easiest
way is to create them via below commands.
	# cd ~/rsu_example
	# rm -rf image_files && mkdir image_files
	# for version in {0..3}
	  do
		quartus_pfg -c sof_files/ghrd_hps.$version.sof image_files/ghrd_hps.$version.rpd -o mode=ASX4 -o start_address=0x00000 -o bitswap=ON
	  done

The following files will be created:
~/rsu_example/image_files/ghrd_hps.0.rpd
~/rsu_example/image_files/ghrd_hps.1.rpd
~/rsu_example/image_files/ghrd_hps.2.rpd
~/rsu_example/image_files/ghrd_hps.3.rpd

9.8 Building ZLIB
-----------------
The ZLIB is required by LIBRSU and it is also built when building intel-socfpga BSP project.
It will be in directory <project dir>/build/tmp/work/cortexa53-wrs-linux/zlib

9.9 Building LIBRSU and RSU Client
----------------------------------
The LIBRSU and the example client application are also built when building intel-socfpga BSP project.
They will be in directory <project dir>/build/tmp/work/cortexa53-wrs-linux/intel-rsu

9.10 Building the SD Card Image
-------------------------------
The bitstream containing the FPGA image and the FSBL is stored in flash,
but the SSBL(u-boot.itb), kernel image, dtb and rootfs will be stored in SD card.
The SD card images(wic files) are also built when building intel-socfpga BSP project.
For Stratix10 platform
<project dir>/build/tmp/deploy/images/intel-socfpga-64/wrlinux-image-std-intel-socfpga-64.rootfs-stratix10-socdk-mmc.wic
For Agilex platform
<project dir>/build/tmp/deploy/images/intel-socfpga-64/wrlinux-image-std-intel-socfpga-64.rootfs-agilex-socdk-mmc.wic

Note:
The Remote Update Production Images(ghrd_hps.0/1/2/3.rpd) need to be copied into rootfs manually.

9.11 Burn the initial image into qspi nor-flash
-----------------------------------------------
For Stratix10 platform
1) Make sure to insert qspi nor-flash card onto the S10 SoC Development Kit, connect with J14.

2) Configure the S10 SoC Development Kit DIP switch as follow, and then power on board.
	SW1: 1:OFF, 2-8:ON
	SW2: 1:ON 2:ON 3: ON 4: OFF
	SW3: all OFF
	SW4: 1:ON 2:OFF 3:OFF 4:ON

For Agilex platform
1) Make sure to insert qspi nor-flash card onto the Agilex SoC Development Kit, connect with J10.

2) Configure the Agilex SoC Development Kit DIP switch as follow, and then power on board.
	SW1: ON-ON-ON-ON
	SW2: all OFF
	SW3: OFF-OFF-ON-ON-ON-ON
	SW4: OFF-OFF-OFF-ON
	SW5: all OFF
	SW6: OFF-OFF-OFF-ON
	SW9: OFF-OFF
	SW10: OFF-ON

3) Start Quartus Programmer tool by running below command.
	# quartus_pgmw

4) Click on Hardware Setup then double-click on the Stratix 10L/Agilex SI SoC DevKit to select it,
   and then click Close.

5) Click Auto Detect and select 1SX280LU3/AGFB014R24B device when prompted, and then click OK.

6) In the Quartus Programmer window, select the device, right-click it, and then select the Change File option.

7) Select the initial_image.jic file then click Open.

8) Click on the Program/Configure and Verify check-box.

9) Click the Start button to start burning into the QSPI flash. The Programmer will configure the device with
   the flash loader firstly, and then erase the device, at last, program the jic file and verify whether the file
   was written correctly.

10) After burning over, Go to File > Save As.. to save the current configuration as ~/rsu_example/initial_image.cdf.
   The file would be useful for writing again to flash without having to use the GUI by running the following command:
	# quartus_pgm initial_image.cdf

9.12 Run remote system update example
-------------------------------------

9.12.1 Run RSU feature from u-boot
----------------------------------
1) Write the SD card image wrlinux-image-std-intel-socfpga-64.rootfs-<stratix10/agilex>-socdk-mmc.wic
   to a SD card with dd command, and then install the SD card onto the Stratix10/Agilex HPS daughtercard.
   Customer also can load kernel, dtb and rootfs from other media(for example, network)

For Stratix10 platform
2) Configure the S10 SoC Development Kit DIP switch as below, so that load FSBL from QSPI:
	SW1: 1:OFF, 2-8:ON
	SW2: 1:ON 2:OFF 3:OFF 4: OFF
	SW3: all OFF
	SW4: 1:ON 2:OFF 3:OFF 4:ON

For Agilex platform
2) Configure the Agilex SoC Development Kit DIP switch as below, so that load FSBL from QSPI:
	SW1: ON-OFF-OFF-ON
	SW2: all OFF
	SW3: OFF-OFF-ON-ON-ON-ON
	SW4: OFF-OFF-OFF-ON
	SW5: all OFF
	SW6: OFF-OFF-OFF-ON
	SW9: OFF-OFF
	SW10: OFF-ON

3) Power on Stratix10/Agilex development board, at the serial console, press any key to enter u-boot command line.

4) Run "rsu list" command to display the RSU partitions, CPBs, the currently running image and the status:
	SOCFPGA_STRATIX10/AGILEX # rsu list
	RSU: Remote System Update Status
	Current Image   : 0x01000000
	Last Fail Image : 0x00000000
	State           : 0x00000000
	Version         : 0x00000202
	Error location  : 0x00000000
	Error details   : 0x00000000
	Retry counter   : 0x00000000
	RSU: Sub-partition table 0 offset 0x00910000
	RSU: Sub-partition table 1 offset 0x00918000
	SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
	RSU: Sub-partition table content
	       BOOT_INFO        Offset: 0x0000000000000000      Length: 0x00110000      Flag : 0x00000003(Stratix10)
	       BOOT_INFO        Offset: 0x0000000000000000      Length: 0x00210000      Flag : 0x00000003(Agilex)
	   FACTORY_IMAGE        Offset: 0x0000000000110000      Length: 0x00800000      Flag : 0x00000003(Stratix10)
	   FACTORY_IMAGE        Offset: 0x0000000000210000      Length: 0x00800000      Flag : 0x00000003(Agilex)
		      P1        Offset: 0x0000000001000000      Length: 0x01000000      Flag : 0x00000000
		    SPT0        Offset: 0x0000000000910000      Length: 0x00008000      Flag : 0x00000001
		    SPT1        Offset: 0x0000000000918000      Length: 0x00008000      Flag : 0x00000001
		    CPB0        Offset: 0x0000000000920000      Length: 0x00008000      Flag : 0x00000001
		    CPB1        Offset: 0x0000000000928000      Length: 0x00008000      Flag : 0x00000001
		      P2        Offset: 0x0000000002000000      Length: 0x01000000      Flag : 0x00000000
		      P3        Offset: 0x0000000003000000      Length: 0x01000000      Flag : 0x00000000
	RSU: CMF pointer block offset 0x00920000
	RSU: CMF pointer block's image pointer list
	Priority 1 Offset: 0x0000000001000000 nslot: 0

The above listing shows what we expected: that we have one factory image, and three production image slots,
with just P1 being used, there are no errors, and the currently loaded image is P1.

5) At the u-uoot console, run the command "rsu update 0x0110000" to tell SDM to load the factory image next time.
   The console will show as bekow:
	For Stratix10 platform
	SOCFPGA_STRATIX10 # rsu update 0x0110000

	RSU: RSU update to 0x0000000000110000
	U-Boot SPL 2022.10 (Mar 20 2023 - 03:03:15 +0000)
	Reset state: Cold
	MPU         1000000 kHz
	L3 main     400000 kHz
	Main VCO    2000000 kHz
	Per VCO     2000000 kHz
	EOSC1       25000 kHz
	HPS MMC     50000 kHz
	UART        100000 kHz
	DDR: 4096 MiB
	SDRAM-ECC: Initialized success with 1195 ms
	...
	SOCFPGA_STRATIX10 #

	For Agilex platform
	SOCFPGA_AGILEX # rsu update 0x0210000

	U-Boot SPL 2022.10 (Mar 20 2023 - 03:03:15 +0000)
	Reset state: Cold
	MPU          1200000 kHz
	L4 Main       400000 kHz
	L4 sys free   100000 kHz
	L4 MP         200000 kHz
	L4 SP         100000 kHz
	SDMMC          50000 kHz
	DDR: 8192 MiB
	SDRAM-ECC: Initialized success with 1725 ms
	...
	SOCFPGA_AGILEX #

6) Run the command "rsu list" again to check the new status:
	SOCFPGA_STRATIX10/AGILEX # rsu list
	RSU: Remote System Update Status
	Current Image   : 0x00110000(Stratix10)
	Current Image   : 0x00210000(Agilex)
	Last Fail Image : 0x00000000
	State           : 0x00000000
	Version         : 0x00000000
	Error locaton   : 0x00000000
	Error details   : 0x00000000
	RSU: Sub-partition table 0 offset 0x00910000
	RSU: Sub-partition table 1 offset 0x00918000
	SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
	RSU: Sub-partition table content
	       BOOT_INFO        Offset: 0x0000000000000000      Length: 0x00110000      Flag : 0x00000003(Stratix10)
	       BOOT_INFO        Offset: 0x0000000000000000      Length: 0x00210000      Flag : 0x00000003(Agilex)
	   FACTORY_IMAGE        Offset: 0x0000000000110000      Length: 0x00800000      Flag : 0x00000003(Stratix10)
	   FACTORY_IMAGE        Offset: 0x0000000000210000      Length: 0x00800000      Flag : 0x00000003(Agilex)
		      P1        Offset: 0x0000000001000000      Length: 0x01000000      Flag : 0x00000000
		    SPT0        Offset: 0x0000000000910000      Length: 0x00008000      Flag : 0x00000001
		    SPT1        Offset: 0x0000000000918000      Length: 0x00008000      Flag : 0x00000001
		    CPB0        Offset: 0x0000000000920000      Length: 0x00008000      Flag : 0x00000001
		    CPB1        Offset: 0x0000000000928000      Length: 0x00008000      Flag : 0x00000001
		      P2        Offset: 0x0000000002000000      Length: 0x01000000      Flag : 0x00000000
		      P3        Offset: 0x0000000003000000      Length: 0x01000000      Flag : 0x00000000
	RSU: CMF pointer block offset 0x00920000
	RSU: CMF pointer block's image pointer list
	Priority 1 Offset: 0x0000000001000000 nslot: 0

The status is basically as before, just that the currently running image is now listed as the factory image.

9.12.2 Run RSU feature from linux
---------------------------------
1) Power cycle the board until boot up linux system completely.

2) Log in system using "root" as user name. The password is also "root" if required.

3) Display the currently loaded image and the status by looking at the sysfs files created by the driver.
	# cd /sys/devices/platform/stratix10-rsu.0
	# cat current_image
	0x01000000
	# cat error_details
	0x00000000
	# cat error_location
	0x00000000
	# cat state
	0x00000000
	# cat version
	0x00000202
	# cat fail_image
	0x00000000

4) Set reloading the factory image on next time booting up
	# cd /sys/devices/platform/stratix10-rsu.0
	For Stratix10 platform
	# printf %i 0x0110000 > reboot_image
	For Agilex platform
	# printf %i 0x0210000 > reboot_image

5) reboot system
	# reboot

6) Log in system, and check remote system update status from sysfs:
	# cd /sys/devices/platform/stratix10-rsu.0

	For Stratix10 platform
	# cat current_image
	0x00110000

	For Agilex platform
	# cat current_image
	0x00210000

	# cat error_details
	0x00000000
	# cat error_location
	0x00000000
	# cat state
	0x00000000
	# cat fail_image
	0x00000000

9.12.3 Run RSU feature from RSU Client Application
--------------------------------------------------
1) Power cycle the board until boot up linux system completely.

2) Log in system using "root" as user name. The password is also "root" if required.

3) Run the rsu_client without parameters, to display its help message
	# rsu_client
	--- RSU app usage ---
	-c|--count                        get the number of slots
	-l|--list slot_num                list the attribute info from the selected slot
	-z|--size slot_num                get the slot size in bytes
	-p|--priority slot_num            get the priority of the selected slot
	-E|--enable slot_num              set the selected slot as the highest priority
	-D|--disable slot_num             disable selected slot but to not erase it
	-r|--request slot_num             request the selected slot to be loaded after the next reboot
	-R|--request-factory              request the factory image to be loaded after the next reboot
	-e|--erase slot_num               erase app image from the selected slot
	-a|--add file_name -s|--slot slot_num  add a new app image to the selected slot
	-u|--add-factory-update file_name -s|--slot slot_num  add a new factory update image to the selected slot
	-A|--add-raw file_name -s|--slot slot_num  add a new raw image to the selected slot
	-v|--verify file_name -s|--slot slot_num  verify app image on the selected slot
	-V|--verify-raw file_name -s|--slot slot_num  verify raw image on the selected slot
	-f|--copy file_name -s|--slot slot_num  read the data in a selected slot then write to a file
	-g|--log                          print the status log
	-n|--notify value                 report software state
	-C|--clear-error-status           clear errors from the log
	-Z|--reset-retry-counter          reset current retry counter
	-m|--display-dcmf-version         print DCMF version
	-y|--display-dcmf-status          print DCMF status
	-x|--display-max-retry            print max_retry parameter
	-t|--create-slot slot_name -S|--address slot_address -L|--length slot_size  create a new slot using unallocated space
	-d|--delete-slot slot_num         delete selected slot, freeing up allocated space
	-W|--restore-spt file_name        restore spt from a file
	-X|--save-spt file_name           save spt to a file
	-b|--create-empty-cpb             create a empty cpb
	-B|--restore-cpb file_name        restore cpb from a file
	-P|--save-cpb file_name           save cpb to a file
	-k|--check-running-factory        check if currently running the factory image
	-h|--help                         show usage message

4) Run rsu client commands that display information about the slots
	# rsu_client --count
	number of slots is 3
	Operation completed

	# rsu_client --list 0
	      NAME: P1
	    OFFSET: 0x0000000001000000
	      SIZE: 0x01000000
	  PRIORITY: 1
	Operation completed

	# rsu_client --list 1
	      NAME: P2
	    OFFSET: 0x0000000002000000
	      SIZE: 0x01000000
	  PRIORITY: [disabled]
	Operation completed

	# rsu_client --list 2
	      NAME: P3
	    OFFSET: 0x0000000003000000
	      SIZE: 0x01000000
	  PRIORITY: [disabled]
	Operation completed

6) Run rsu client command that displays the current status
	# rsu_client --log
	      VERSION: 0x00000202
		STATE: 0x00000000
	CURRENT IMAGE: 0x0000000001000000
	   FAIL IMAGE: 0x0000000000000000
	    ERROR LOC: 0x00000000
	ERROR DETAILS: 0x00000000
	Operation completed

7) Add the ghrd_hps.2.rpd remote update image to slot 2 and ghrd_hps.3.rpd to slot 1:
	# rsu_client --add ghrd_hps.2.rpd --slot 2
	Operation completed

	# rsu_client --add ghrd_hps.3.rpd --slot 1
	Operation completed

8) List again the slots, it will show the expected priorities, showing the order in which
   the update images were written, with the most recently written having the highest priority.
   The smaller the value, the higher the priority
	# rsu_client --list 0
	      NAME: P1
	    OFFSET: 0x0000000001000000
	      SIZE: 0x01000000
	  PRIORITY: 3
	Operation completed
	# rsu_client --list 1
	      NAME: P2
	    OFFSET: 0x0000000002000000
	      SIZE: 0x01000000
	  PRIORITY: 1
	Operation completed
	# rsu_client --list 2
	      NAME: P3
	    OFFSET: 0x0000000003000000
	      SIZE: 0x01000000
	  PRIORITY: 2
	Operation completed

9) Power cycle the board, boot system. And then display the status,
   it will show the P2 image running, as expected:
	# rsu_client --log
	      VERSION: 0x00000202
		STATE: 0x00000000
	CURRENT IMAGE: 0x0000000002000000
	   FAIL IMAGE: 0x0000000000000000
	    ERROR LOC: 0x00000000
	ERROR DETAILS: 0x00000000
	Operation completed

10) Tell SDM to load the P3 image on next time booting up
	# rsu_client --request 2
	Operation completed

11) reboot system.
	# reboot

12) Log in system, And then display the RSU status:
	# rsu_client --log
	      VERSION: 0x00000202
		STATE: 0x00000000
	CURRENT IMAGE: 0x0000000003000000
	   FAIL IMAGE: 0x0000000000000000
	    ERROR LOC: 0x00000000
	ERROR DETAILS: 0x00000000
	Operation completed


10. Memory ECC
==============

10.1 Enable ECC feature
-----------------------

Please refer to below link:
https://rocketboards.org/foswiki/Documentation/S10GSRDEnableHPS_DDR_ECC

If ECC feature is enabled, when board boots up, there is below output information.
SDRAM-ECC: Initialized success with 1343 ms

10.2 Verify ECC feature
-----------------------

Check whether ECC feature take effect, please follow below steps.

1) Enable kernel configure and then rebuild kernel
	CONFIG_EDAC_DEBUG=y

2) Boot up system and then login.

3) Check the error count
	# cat /sys/devices/system/edac/sdramedac/sdramedac0/ce_count
	0 (It should be zero)

4) Inject error
	# echo "C" > /sys/kernel/debug/edac/sdramedac/altr_trigger
	EDAC DEVICE0: CE: Altera ECC Manager instance: sdramedac0 block: sdramedac0 count: 1 'sdramedac'

5) Check the error count again
	# cat /sys/devices/system/edac/sdramedac/sdramedac0/ce_count
	1 (It should be incremented by 1)

11. kexec/kdump
===============

You need to add feature/kexec,feature/kdump templates support as follow:

	./wrlinux-x/setup.sh --machines intel-socfpga-64 --templates feature/kexec,feature/kdump

11.1 kexec
---------

	kexec -l  /root/Image.gz --append="`cat /proc/cmdline`"
	kexec -e

11.2 kdump
---------

Add crashkernel=256M@256M to the kernel cmdline
   kexec -p /root/Image.gz --append="$your-bootcmd"
   echo c > /proc/sysrq-trigger

Note:
1) Before booting the second kernel, add "maxcpus=1" to the boot parameter.
2) When FCS is enabled, more memory is needed, a recommended crashkernel size is "1024M".

For more detailed info about kdump, refer to Documentation/kdump/kdump.txt
in the kernel source tree.

12. PCIe(Stratix10 only)
========================

12.1 PCIe Introduction
----------------------

PCIe feature is implemented in FPGA side. It is compliant with PCI Express Base Specification 3.0.
This IP core combines the functionality of previous Avalon Memory-Mapped (Avalon-MM) and Avalon-MM
direct memory access (DMA) interfaces.

Detail description, please refer to https://rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI

12.2 PCIe Verification
----------------------

There is a PCIe port on stratix10 board J35.
The following PCIe peripheral:

	Intel 1G Single Port Ethernet Desktop Adapter

 is used to verify PCIe feature with the following steps:

Simply add line as follows to ${buildprj}/build/conf/local.conf:

	KERNEL_FEATURES:append = " features/intel-e1xxxx/intel-e1xxxx.scc"

Intel E1000E NIC driver will be built in kernel Image

Build Image

	# bitbake wrlinux-image-std

Get FPGA image with PCIe feature from below below:
https://releases.rocketboards.org/2021.04/pcie/s10_pcie/

Generate sof file and program it into board with Quartus programmer tool,
and then run below commands to boot up system.

	SOCFPGA_STRATIX10 # run fatscript
	SOCFPGA_STRATIX10 # tftp 0x2000000 "/<tftp root>/Image"
	SOCFPGA_STRATIX10 # tftp 0x8000000 "/<tftp root>/socfpga_stratix10_socdk_pcie.dtb"
	SOCFPGA_STRATIX10 # run linux_qspi_enable
	SOCFPGA_STRATIX10 # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
				  nfsroot=<nfs server>:<nfs root>,nolock \
				  ip=<target IP>::<gateway>:<netmask>::eth0:off
	SOCFPGA_STRATIX10 # booti 0x2000000 - 0x8000000

After system boots up, execute the following commands to verify PCIe interface:

	# ifconfig
	# dhcpcd eth1
	# ping <ip address> -I eth1 -c 5

Note: When run PCIe feature, please use socfpga_stratix10_socdk_pcie.dtb file.


13. FPGA SGMII Ethernet
=======================

13.1 FPGA SGMII Ethernet on Stratix10 platform
----------------------------------------------

13.1.1 SGMII Ethernet Introduction
----------------------------------

SGMII Ethernet feature is implemented in FPGA side.
User can download the pre-build FPGA image or FPGA project from below link:
https://releases.rocketboards.org/release/2021.04/.

About how to build FPGA project and apply the FPGA image, please refer to below links:
https://rocketboards.org/foswiki/Documentation/Stratix10SoCGSRD
https://www.intel.com/content/www/us/en/programmable/documentation/kqx1502122862454.html

13.1.2 SGMII Ethernet Verification
----------------------------------

There are 2 SGMII ethernet ports on stratix10 board J3 and J4. Connect them to a switch.

Build Image

	# bitbake wrlinux-image-std

Power on board, program FPGA image into flash with Quartus programmer tool,
and then run below commands to boot up system.

	SOCFPGA_STRATIX10 # run fatscript
	SOCFPGA_STRATIX10 # tftp 0x2000000 "/<tftp root>/Image"
	SOCFPGA_STRATIX10 # tftp 0x8000000 "/<tftp root>/socfpga_stratix10_socdk_sgmii.dtb"
	SOCFPGA_STRATIX10 # run linux_qspi_enable
	SOCFPGA_STRATIX10 # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
				  nfsroot=<nfs server>:<nfs root>,nolock \
				  ip=<target IP>::<gateway>:<netmask>::eth0:off
	SOCFPGA_STRATIX10 # booti 0x2000000 - 0x8000000

After system boots up, execute the following commands to verify sgmii interface:

	# ifconfig -a
	# dhcpcd eth1
	# dhcpcd eth2
	# ping <ip address> -I eth1 -c 5
	# ping <ip address> -I eth2 -c 5

Note: When run FPGA SGMII ethernet feature, please use socfpga_stratix10_socdk_sgmii.dtb file.

13.2 FPGA SGMII Ethernet on Agilex platform
-------------------------------------------

13.2.1 SGMII Ethernet Introduction
----------------------------------

SGMII Ethernet feature is implemented in FPGA side.
User can download the pre-build FPGA image or FPGA project from below link:
https://releases.rocketboards.org/release/2021.11/.

About how to build FPGA project and apply the FPGA image, please refer to below links:
https://rocketboards.org/foswiki/Documentation/AgilexSoCGSRD
https://www.intel.com/content/www/us/en/docs/programmable/683389/21-4/introduction.html

13.1.2 SGMII Ethernet Verification
----------------------------------

There is on SGMII ethernet ports on Agilex board J15. Connect it to a switch.

Build Image

	# bitbake wrlinux-image-std

Power on board, program FPGA image into flash with Quartus programmer tool,
and then run below commands to boot up system.


	SOCFPGA_AGILEX # run fpgaload
	SOCFPGA_AGILEX # tftp 0x2000000 "/<tftp root>/Image"
	SOCFPGA_AGILEX # tftp 0x8000000 "/<tftp root>/socfpga_agilex_socdk_nand_sgmii.dtb"
	SOCFPGA_AGILEX # run linux_qspi_enable
	SOCFPGA_AGILEX # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
				  nfsroot=<nfs server>:<nfs root>,nolock \
				  ip=<target IP>::<gateway>:<netmask>::eth0:off
	SOCFPGA_AGILEX # booti 0x2000000 - 0x8000000

After system boots up, execute the following commands to verify sgmii interface:

	# ifconfig -a
	# dhcpcd eth1
	# ping <ip address> -I eth1 -c 5

Note1: When run FPGA SGMII ethernet feature, please use socfpga_agilex_socdk(_nand)_sgmii.dtb file.

14. FPGA GPIO
=============

14.1 FPGA GPIO on Stratix10 platform
------------------------------------

14.1.1 FPGA GPIO Introduction
-----------------------------

FPGA GPIO feature is implemented in GHRD(golden hardware reference design) FPGA image.
User can download the pre-build FPGA image or FPGA project from below link:
https://releases.rocketboards.org/release/2021.11/.

About how to build FPGA project and apply the FPGA image, please refer to below links:
https://rocketboards.org/foswiki/Documentation/Stratix10SoCGSRD
https://www.intel.com/content/www/us/en/programmable/documentation/kqx1502122862454.html

14.1.2 FPGA GPIO Verification
-----------------------------

There are 4 User FPGA DIPSWs on stratix10 board from SW3.1 to SW3.4, they are all in off status by default.
There are 4 User FPGA BUTTONs on stratix10 board from S4 to S7.
There are 4 User FPGA LEDs on stratix10 board from LED0 to LED3, but the LED3 is already used by GHRD FPGA image.

Build Image

	# bitbake wrlinux-image-std

Power on board, program FPGA image into flash with Quartus programmer tool,
and then run below commands to boot up system.

	SOCFPGA_STRATIX10 # run fatscript
	SOCFPGA_STRATIX10 # tftp 0x2000000 "/<tftp root>/Image"
	SOCFPGA_STRATIX10 # tftp 0x8000000 "/<tftp root>/socfpga_stratix10_socdk_ghrd.dtb"
	SOCFPGA_STRATIX10 # run linux_qspi_enable
	SOCFPGA_STRATIX10 # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
				  nfsroot=<nfs server>:<nfs root>,nolock \
				  ip=<target IP>::<gateway>:<netmask>::eth0:off
	SOCFPGA_STRATIX10 # booti 0x2000000 - 0x8000000

After system boots up, verify FPGA GPIO feature with below sections.

14.1.2.1 FPGA LED
-----------------

Run below command to turn on/off the FPGA LEDs.
- To turn on/off FPGA_LED0(D21):
	# echo 1 > /sys/class/leds/fpga_led0/brightness
	# echo 0 > /sys/class/leds/fpga_led0/brightness

- To turn on/off FPGA_LED1(D23):
	# echo 1 > /sys/class/leds/fpga_led1/brightness
	# echo 0 > /sys/class/leds/fpga_led1/brightness

- To turn on/off FPGA_LED2(D25):
	# echo 1 > /sys/class/leds/fpga_led2/brightness
	# echo 0 > /sys/class/leds/fpga_led2/brightness

Run below command to start/stop blinking FPGA LEDs.
- To start/stop blinking FPGA_LED0(D21):
	# echo timer > /sys/class/leds/fpga_led0/trigger
	# echo none > /sys/class/leds/fpga_led0/trigger

- To start/stop blinking FPGA_LED1(D23):
	# echo timer > /sys/class/leds/fpga_led1/trigger
	# echo none > /sys/class/leds/fpga_led1/trigger

- To start/stop blinking FPGA_LED2(D25):
	# echo timer > /sys/class/leds/fpga_led2/trigger
	# echo none > /sys/class/leds/fpga_led2/trigger

Note: When run FPGA GPIO feature, please use socfpga_stratix10_socdk_ghrd.dtb file.

14.2 FPGA GPIO on Agilex platform
---------------------------------

14.2.1 FPGA GPIO Introduction
-----------------------------

FPGA GPIO feature is implemented in GHRD(golden hardware reference design) FPGA image.
User can download the pre-build FPGA image or FPGA project from below link:
https://releases.rocketboards.org/release/2021.11/.

About how to build FPGA project and apply the FPGA image, please refer to below links:
https://rocketboards.org/foswiki/Documentation/AgilexSoCGSRD
https://www.intel.com/content/www/us/en/docs/programmable/683389/21-4/introduction.html

14.2.2 FPGA GPIO Verification
-----------------------------

There are 4 User FPGA DIPSWs on Agilex board from SW2.1 to SW2.4, they are all in off status by default.
There are 4 User FPGA BUTTONs on Agilex board from S1 to S4.
There are 4 User FPGA LEDs on Agilex board from LED0 to LED3, but the LED3 is already used by GHRD FPGA image.

Build Image

	# bitbake wrlinux-image-std

Power on board, program FPGA image into flash with Quartus programmer tool,
and then run below commands to boot up system.

	SOCFPGA_AGILEX # run fpgaload
	SOCFPGA_AGILEX # tftp 0x2000000 "/<tftp root>/Image"
	SOCFPGA_AGILEX # tftp 0x8000000 "/<tftp root>/socfpga_agilex_socdk_nand_ghrd.dtb"
	SOCFPGA_AGILEX # run linux_qspi_enable
	SOCFPGA_AGILEX # setenv bootargs console=ttyS0,115200n8 root=/dev/nfs rw \
				  nfsroot=<nfs server>:<nfs root>,nolock \
				  ip=<target IP>::<gateway>:<netmask>::eth0:off
	SOCFPGA_AGILEX # booti 0x2000000 - 0x8000000

After system boots up, verify FPGA GPIO feature with below sections.

14.2.2.1 FPGA LED
-----------------

Run below command to turn on/off the FPGA LEDs.
- To turn on/off FPGA_LED0(D7):
	# echo 1 > /sys/class/leds/fpga_led0/brightness
	# echo 0 > /sys/class/leds/fpga_led0/brightness

- To turn on/off FPGA_LED1(D8):
	# echo 1 > /sys/class/leds/fpga_led1/brightness
	# echo 0 > /sys/class/leds/fpga_led1/brightness

- To turn on/off FPGA_LED2(D9):
	# echo 1 > /sys/class/leds/fpga_led2/brightness
	# echo 0 > /sys/class/leds/fpga_led2/brightness

Run below command to start/stop blinking FPGA LEDs.
- To start/stop blinking FPGA_LED0(D7):
	# echo timer > /sys/class/leds/fpga_led0/trigger
	# echo none > /sys/class/leds/fpga_led0/trigger

- To start/stop blinking FPGA_LED1(D8):
	# echo timer > /sys/class/leds/fpga_led1/trigger
	# echo none > /sys/class/leds/fpga_led1/trigger

- To start/stop blinking FPGA_LED2(D9):
	# echo timer > /sys/class/leds/fpga_led2/trigger
	# echo none > /sys/class/leds/fpga_led2/trigger

Note: When run FPGA GPIO feature, please use socfpga_agilex_socdk_ghrd.dtb file.


15. Bootloader
==============

15.1 Introduction
-----------------

Now, there are 2 kinds of bootloader mode supported on aarch 64 socfpga platform.
Legacy mode: spl+u-boot, bootrom loads spl, and then spl loads u-boot.
ATF mode: spl+atf+u-boot, bootrom loads spl, and then spl loads bl31, and then bl31 loads u-boot.

Intel recommends customer to use the ATF mode for common aarch64 platform.
Now ATF mode is enabled by default in the current supported u-boot.

15.2 Known issue
----------------

15.2.1 CPU OFF/ON Limitation

When using u-boot v2021.07 ATF mode, there is a limitation of cpu off/on feature.
The cpu0 doesn't support off/on operation, otherwise it causes board reset.
Therefore, creating a patch in kernel to remove the online file interface of cpu0
to avoid board reset even if there is a mistake operation to cpu0.

15.3  Build U-Boot
------------------

By default, the u-boot image is compiled and installed. If you want u-boot to be manually
compiled separately, use the following command：

        # bitbake u-boot-socfpga

16. Boot System From NAND Flash(Agilex only)
============================================

Please follow below steps to implement booting system from NAND flash.

16.1 Prerequisites
------------------

16.1.1 Software Preparation
---------------------------

Please download below 2 tools from https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html, linux version.
- Quartus Prime Pro Edition Programmer and Tools v21.3
- Quartus Prime Pro Edition Software v21.3
Note: Please apply for license for building Stratix10/Agilex *.sof file.
      Customer also can get the pre-build *.sof file from https://releases.rocketboards.org/release/2021.11/.

Please download Arm Development Studio for Intel SoC FPGA from https://fpgasoftware.intel.com/armds/

16.1.2 Hardware Preparation
---------------------------

Connect NAND/eMMC Daughtercard with Agilex mother board, and then set jumper as below:
J2 	unpopulated
J9 	unpopulated
J10 	populated 2-3
J11 	populated 1-2

16.2 Building Hardware Design
-----------------------------

Run below commands step by step

	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# mkdir hardware_designs
	# git clone https://github.com/altera-opensource/ghrd-socfpga.git
	# cd ghrd-socfpga
	# git checkout -b QPDS-21.3pro-21.1std QPDS-21.3pro-21.1std
	# cp -r agilex_soc_devkit_ghrd ../hardware_designs
	# cd ../hardware_designs/agilex_soc_devkit_ghrd
	# sed -i 's/DAUGHTER_CARD .*= devkit_dc_oobe/DAUGHTER_CARD ?= devkit_dc_nand/g' Makefile
	# sed -i 's/QUARTUS_DEVICE .*= AGFB014R24A3E3VR0/QUARTUS_DEVICE ?= AGFB014R24B2E2V/g' Makefile
	# make clean && make scrub_clean && rm -rf output_files
	# export IP_ROOTDIR=<path-to-quartus>/intelFPGA_pro/21.3/ip
	# make generate_from_tcl
	# make sof

After building, there will be the following SOF files:
s10_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof

Note: set HPS_ENABLE_SGMII as 0 in below 2 files, because the sgmii feature needs special license on Agilex platform.
      agilex_soc_devkit_ghrd/Makefile
      agilex_soc_devkit_ghrd/board/board_devkit_make_config.inc

16.3 Building U-Boot
--------------------

NAND flash u-boot for Agilex is also built when building intel-socfpga BSP project, it will be in directory
<project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_agilex_nand_defconfig


16.4 Building FPGA Image
------------------------

Run below commands step by step

	# mkdir fpga_image
	# cd fpga_image
	# cp <project dir>/build/tmp/deploy/images/intel-socfpga-64/socfpga_agilex_nand_defconfig/u-boot-spl-dtb.hex ./
	# cp <hardware design dir>/s10_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof ./
	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# quartus_pfg -c ghrd_agfb014r24b2e2v.sof flash_image_nand.jic -o device=MT25QU02G -o flash_loader=AGFB014R24B -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4

The FPGA Image(flash_image_nand.jic) is generated.

16.5 Building FPGA Configuration File
-------------------------------------

Run below commands step by step

	# cd fpga_image
	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# quartus_pfg -c -o hps_path=u-boot-spl-dtb.hex ghrd_agfb014r24b2e2v.sof ghrd_agfb014r24b2e2v_hps_nand.sof
	# quartus_pfg -c -o hps=on ghrd_agfb014r24b2e2v_hps_nand.sof ghrd_nand.rbf

The FPGA configuration file(ghrd_nand.core.rbf) is generated.

16.6 Building Ubifs Image
-------------------------

Run below commands step by step

	# mkdir nand-rootfs
	# cp <project dir>/build/tmp/deploy/images/intel-socfpga-64/wrlinux-image-std-intel-socfpga-64.tar.bz2 ./
	# tar jxvf wrlinux-image-std-intel-socfpga-64.tar.bz2
	# rm wrlinux-image-std-intel-socfpga-64.tar.bz2
	# cd ..
	# mkfs.ubifs -r nand-rootfs -m 2048 -e 126976 -c 4096 -o ubifs.img

The ubifs image(ubifs.img) is generated.

16.7 Burn FPGA Image Into QSPI Flash
------------------------------------

Connect CN1 to PC host with usb cable, and then follow below steps.

16.7.1 Enable JTAG
------------------

Set SW1 as below status, and then Power on the board.

SW1: ON-ON-ON-ON

16.7.2 Program QSPI Flash
-------------------------

	# cd fpga_image
	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# quartus_pgm -c 1 -m jtag -o "pvi;flash_image_nand.jic"

16.7.3 Disable JTAG
-------------------

Power off the board, and then set SW1 as below status.

SW1: ON-OFF-OFF-ON

16.8 Burn Images Into NAND Flash
--------------------------------

At the beginning. there is not any image in NAND flash, so it needs to boot up system with JTAG.

16.8.1 Enable JTAG
------------------

Set SW1 as below status, and then Power on the board.

SW1: ON-ON-ON-ON

16.8.2 Configure the FPGA
-------------------------

	# cd fpga_image
	# cp <hardware design dir>/s10_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof ./
	# <path-to-quartus>/intelFPGA_pro/21.3/nios2eds/nios2_command_shell.sh
	# quartus_pgm --no_banner --mode=jtag -o "p;ghrd_agfb014r24b2e2v_hps_debug.sof"

16.8.3 Create Debugger Script
-----------------------------

	# cd fpga_image
	# cat <<EOT > run-u-boot.ds
	  interrupt
	  restore "u-boot-socfpga/spl/u-boot-spl-dtb.bin" binary 0xFFE00000
	  loadfile "u-boot-socfpga/spl/u-boot-spl"
	  core 1
	  set \$PC = \$ENTRYPOINT
	  core 2
	  set \$PC = \$ENTRYPOINT
	  core 3
	  set \$PC = \$ENTRYPOINT
	  core 0
	  set \$PC = \$ENTRYPOINT
	  thbreak board_boot_order
	  continue
	  wait
	  set spl_boot_list[0]=0
	  set \$PC=\$LR
	  restore "u-boot-socfpga/u-boot.itb" binary 0x2000000
	  continue
	  EOT

16.8.4 Determine Cable Connection Info
--------------------------------------

Run jtagconfig to determine the details about the Intel FPGA cable connection.

	# jtagconfig
	1) Agilex SI/SoC Dev Kit [1-1]
	  C341A0DD   AGFB014R24(A|B)
	  031830DD   10M16S(A|C|L)

16.8.5 Run Debugger Script
--------------------------

Run the debugger script with below command, using the connection parameters reported above by jtagconfig command.

	# cd fpga_image
	# mkdir u-boot-socfpga
	# mkdir u-boot-socfpga/spl
	# cp <project dir>build/tmp/work/intel_socfpga_64-wrs-linux/u-boot-socfpga/1_v2022.10+gitAUTOINC+61ae22e548-r0/build/socfpga_agilex_nand_defconfig/u-boot.itb ./u-boot-socfpga
	# cp <project dir>build/tmp/work/intel_socfpga_64-wrs-linux/u-boot-socfpga/1_v2022.10+gitAUTOINC+61ae22e548-r0/build/socfpga_agilex_nand_defconfig/spl/u-boot-spl ./u-boot-socfpga/spl
	# cp <project dir>build/tmp/work/intel_socfpga_64-wrs-linux/u-boot-socfpga/1_v2022.10+gitAUTOINC+61ae22e548-r0/build/socfpga_agilex_nand_defconfig/spl/u-boot-spl-dtb.bin ./u-boot-socfpga/spl
	# <path-to-developmentstudio>/arm/developmentstudio-2021.1/bin/armdbg  \
	  --cdb-entry="Intel SoC FPGA::Agilex SoC::Bare Metal Debug::Bare Metal Debug::Cortex-A53x4 SMP::Intel FPGA Download Cable"  \
	  --cdb-entry-param="rvi_address=Agilex SI/SoC Dev Kit on localhost [1-1]:Agilex SI/SoC Dev Kit 1-1"  \
	  --continue_on_error=true \
	  --stop_on_connect=false \
	  -s run-u-boot.ds

16.8.6 Burn Images
------------------

The above commands will cause the U-Boot to start running on HPS.
Stop U-Boot counter by pressing any key on the serial console.
And then run below commands step by step.

Note: Setup tftp server firstly.

	# setenv ipaddr <board ip>
	# setenv netmask <netmask>
	# setenv gatewayip <gateway ip>
	# setenv serverip <server ip>
	# tftp 0x2000000 <server ip>:<tftp-dir>/u-boot.itb
	# nand erase.part u-boot
	# nand write 0x2000000 u-boot $filesize
	# nand erase.part root
	# ubi part root
	# ubi createvol kernel 0x3000000 static
	# ubi createvol dtb 0x100000 static
	# ubi createvol fpga 0x800000 static
	# ubi createvol env 0x100000 static
	# ubi createvol rootfs 0x20000000 dynamic
	# tftp 0x2000000 <server ip>:<tftp-dir>/Image
	# ubi writevol 0x2000000 kernel $filesize
	# tftpboot 0x8000000 <server ip>:<tftp-dir>/socfpga_agilex_socdk_nand.dtb
	# ubi writevol 0x8000000 dtb $filesize
	# tftpboot 0x2000000 <server ip>:<tftp-dir>/ghrd_nand.core.rbf
	# ubi writevol 0x2000000 fpga $filesize
	# tftpboot 0x2000000 <server ip>:<tftp-dir>/ubifs.img
	# ubi writevol 0x2000000 rootfs $filesize

After burning all the images into NAND flash, power off board.

16.8.7 Disable JTAG
-------------------

Set SW1 as below status.

SW1: ON-OFF-OFF-ON

16.8.8 Boot System From NAND Flash
----------------------------------

Power on board, system will boot up from NAND flash.


17. suspend/resume
==================

Both Stratix10 and Agilex platforms don't support for deep level suspend, because they all don't
implement system suspend both in legacy and atf mode bootloader. So, they can only enter idle level.
Detail example as below, using serial to wakeup system.

	# echo s2idle > /sys/power/mem_sleep
	# echo enabled > /sys/bus/platform/drivers/dw-apb-uart/ffc02000.serial/tty/ttyS0/power/wakeup
	# echo mem > /sys/power/state
	system enter suspend status
	press any key to wake up system

Note: add no_console_suspend in bootargs if using serial to wakeup system.