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Error when making inference on ZCU102 - Tutorial yolov4 #305

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vongracia opened this issue Sep 29, 2022 · 1 comment
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Error when making inference on ZCU102 - Tutorial yolov4 #305

vongracia opened this issue Sep 29, 2022 · 1 comment

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@vongracia
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Hi folks,

I've followed this https://github.com/Xilinx/Vitis-AI-Tutorials/tree/1.4/Design_Tutorials/07-yolov4-tutorial (using ./docker_run.sh xilinx/vitis-ai-cpu:1.4.916 because it requires Vitis 1.4) to quantize and compile a darknet trained yolov4 on my custom data. I tried the caffe tutorial. When i get to the final step to make the inference on the FPGA ZCU102 I get this error:

[libprotobuf ERROR google/protobuf/text_format.cc:323] Error parsing text-format vitis.ai.proto.DpuModelParamList: 1:5: Message type "vitis.ai.proto.DpuModelParamList" has no field named "name".
WARNING: Logging before InitGoogleLogging() is written to STDERR
F1119 17:30:48.142455 1033 configurable_dpu_task_imp.cpp:142] Check failed: ok cannot parse config file. config_file=dpu_yolov4_voc_andante.prototxt
*** Check failure stack trace: ***
Aborted

Do you know what this mean? Please give me a hand, it driving me crazy.

Here the 4 files (file.prototxt, file.xmodel, md5sum.txt, meta.json) produced at the end. I used only the prototxt and xmodel to run the inference: https://wetransfer.com/downloads/032432a82712d0d99a67cc0c2d6beabb20220928144618/267f8e

Please take a look, maybe you can find something
Thanks

@imrickysu
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Hi @vongracia, could you ask this question in the Vitis-AI tutorial repo or Xilinx forums? This issue doesn't seem to relate to the Vitis Acceleration flow. Engineers watching these two places may help you.

CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
6dfe46d Merge pull request Xilinx#344 from changg/fix_cr1128852
90e6901 fix CR-1128852
8d372c8 Merge pull request Xilinx#342 from Zhenhong/next
415b846 Merge pull request Xilinx#341 from sibow/next
4f1a8a2 change platform for L2 and L1
e7fd42b add result check
76ef1f8 update overview
34d4e0b update overview
75b958d Merge pull request Xilinx#337 from Zhenhong/next
5ece73d update tutorial
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c69f5e8 update readme and release notes
ed1f6d8 Merge pull request Xilinx#335 from Zhenhong/next
f92f99a fix wrong connectivity (Xilinx#334)
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a311d95 Merge pull request Xilinx#317 from shengl/next-tutorial
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b1a5fe2 Update demo_start.py
07c8b6e Update demo_start.py
ffdff1e fix golden value check
ae2248e �
8ff83eb Fix u50build crs (Xilinx#329)
b648d94 fix hw build and host error (Xilinx#328)
be919b6 fix error in gradient calculation (Xilinx#327)
e0f566a Merge pull request Xilinx#323 from shengl/next-revert
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5273d05 fix cr
ef1cd05 add explaination for number of csv parser
d632218 revert utils.mk
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64749d3 Merge pull request Xilinx#319 from shengl/next-revert
17c11ee Merge pull request Xilinx#318 from Zhenhong/next
4a3b507 not support auto update Makefile, fix CR-1127263
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6ba3c88 clang_format
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c201b4c remove etl info
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33bdfd2 Merge pull request Xilinx#314 from yuanqian/update
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471d729 update connectivity
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85e3273 Merge pull request Xilinx#312 from leol/fix-seg-fault
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570869a remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831
c9ce4cb Merge remote-tracking branch 'upstream/next' into next
c4f681d Revert "remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831"
205d4ba remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831
80828e7 fix cr, not meet timing
1e6c956 add tutorial.rst for library
9d16cfd replace cflags with clflags (Xilinx#308)
f9271b9 Merge pull request Xilinx#278 from shengl/next-geospatial
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b87a182 move swig & arrow build file to ext folder
b2eb439 Merge pull request Xilinx#306 from Zhenhong/next
0b2fad4 fix CR-1122218
8417203 conv fix (Xilinx#305)
a583923 Merge pull request Xilinx#304 from Zhenhong/next
fdeaea8 decrease clock frequency from 300MHz to 250MHz
23fab12 fix design not meet timing issue CR-1123916
f9dc2c9 reduce instance to fix partially-conflicted nets issue CR-1123132
94957b6 modify size
ca88eab Merge pull request Xilinx#301 from liyuanz/add_time
343bb50 modfiy description.json
ded4f92 add dat folder
a5a06ba adjust file location
16eb6fc remove cmake install
f0799d7 Merge pull request Xilinx#302 from sibow/next
5bc5688 fix code bug
53d611d free buffer
92c937f fix hw_emu bug
5035336 fix hw_emu build bug
736cba4 multithread execute data preparation and kernel computation
8b38898 re-run
bd029af add time
96cfe05 Merge branch 'next' into next-geospatial
bb391ad add database to Jenkinsfile
697e10a change to load-balance; fix 4/8 pu hang issue.
249622a fix swig install bug in jks
1338bc1 add namespace
ce27c16 test jks env
4a31247 test jks
0c6f5ba test jks env
e4c8f84 update
154dae3 update env
e23ad93 install swig
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60e69e7 optimize gcc
0e7170a Merge pull request Xilinx#299 from sibow/next
48eaddb Merge pull request Xilinx#300 from liyuanz/increase
cf41987 Merge pull request Xilinx#295 from leol/fix-CR-1122134
224cb86 add geospatial case with supporting system compiler
1cca005 update cmodel case
977f483 increase time
cf95f3c support index in kernel
177d7d2 fix bug in handling '\n'
18e5404 switch python
e0b2afb replace whiltelist/blacklist to allowlist/blocklist (Xilinx#298)
25e9717 add memory/time for mem/time limit cases (Xilinx#297)
4c5d118 add memory (Xilinx#296)
52ca339 Fix for linking error found in daily regression
29a7c28 Merge pull request Xilinx#289 from sibow/next
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8317d90 add support for u2
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0349d34 increase time (Xilinx#292)
0409239 update L1 input point
57cefc7 Switch ref-code from master to next as they are the same
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3632375 change preprocess mode
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4d11300 Fix the csim/cosim mismatch as uninitilized mem (Xilinx#287)
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518b0c3 Remove redundant C_MODEL flow files + Add comments
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56c2045 update Makefile
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9897a93 Correct the pragma
00463f1 Add json parser API, CSIM passed
415f4fc Clean the unused structs
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242a872 fix https://jira.xilinx.com/browse/CR-1101226
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Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
fb2f08e Merge pull request Xilinx#310 from yuxiangz/encode_mode
572425a update results
8272b1f Merge pull request Xilinx#309 from yuxiangz/encode_mode
34a73a5 update results
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f546bf9 update qei
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e350a16 Merge pull request Xilinx#306 from congt/next
ced7186 [tutorial]correct git checkout next position
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764b078 [foc-sensorless]align with foc, testbench refine
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4578eab [doc] sensor foc refine
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072b954 [doc]refine foc
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620e10e [tutorial]fix path
ba2c022 Merge branch 'next' of https://gitenterprise.xilinx.com/congt/xf_motorcontrol into next
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22ed83f [tutorial]first version
7d5ad26 [sensor] refine sin/cos table from 500 steps to 1000
35ce325 clang formate for host
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9749f1c Refined the B_leading_A for host and added an enum Direction_QEI
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f312213 [foc-sensorless]code refine
37c14e1 Merge branch 'FaaSApps:next' into next
f7cd92d [foc-sensorless]add missing foc_sensorless.hpp and smo.hpp files
b58a312 [foc-sensorless]three interfaces of Vabc for smo added
01ae670 [foc-sensorless]coding style
54aa881 Merge branch 'next' of https://gitenterprise.xilinx.com/congt/xf_motorcontrol into next
6a846e2 [foc-sensorless]fix the axilite address mismatch
590f7c3 Merge pull request Xilinx#296 from yunleiz/next
2311560 [sensor-foc] add both directions simulation test

Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
86f185a Merge pull request Xilinx#306 from RepoOps/rep_8
e2e313d Merge pull request Xilinx#305 from congt/next
f033866 Replace DEVICE with PLATFORM
cac8cb3 Merge branch 'next' of https://gitenterprise.xilinx.com/FaaSApps/xf_codec into next
b223f88 [CR-1156877]fix compile failed in Ubuntu
88768f1 Merge pull request Xilinx#304 from liyuanz/add_fre
874c255 update
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3b10210 Merge pull request Xilinx#303 from liyuanz/next
64e1d1f add mem
48ab684 Merge pull request Xilinx#302 from liyuanz/next
6c67ba8 update

Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
9361096 Merge pull request Xilinx#310 from liyuanz/update_makefile_hls
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742c178 Merge pull request Xilinx#308 from liyuanz/update_makefile
f9cc67a update makefile
269d83d Fix wrong buffer size in HLS tb (Xilinx#307)
6edd579 Add warning to headers; add notice in doc (Xilinx#306)
ba4ca8b Merge pull request Xilinx#305 from liyuanz/add_memory2
15ffcdc update

Co-authored-by: sdausr <sdausr@xilinx.com>
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