Multipliers in separate files #321
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Hi @vrrao01 , it looks like your question is a generic issue, that is not related to a specific Vitis tutorial. Could you please ask this question in Xilinx forums? https://forums.xilinx.com/ |
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Hi @randyh62 , if you in case know that HLS has some configurations can change this behavior, please feel free to comment. |
imrickysu
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You could try the ALLOCATION pragma: |
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6dfe46d Merge pull request Xilinx#344 from changg/fix_cr1128852 90e6901 fix CR-1128852 8d372c8 Merge pull request Xilinx#342 from Zhenhong/next 415b846 Merge pull request Xilinx#341 from sibow/next 4f1a8a2 change platform for L2 and L1 e7fd42b add result check 76ef1f8 update overview 34d4e0b update overview 75b958d Merge pull request Xilinx#337 from Zhenhong/next 5ece73d update tutorial b51d442 Merge pull request Xilinx#336 from Zhenhong/next c69f5e8 update readme and release notes ed1f6d8 Merge pull request Xilinx#335 from Zhenhong/next f92f99a fix wrong connectivity (Xilinx#334) 58e50b7 disable vck190 platform in regression/linearRegressionSGDTrain and clustering/kmeans due to timming issue b3d348a Merge pull request Xilinx#332 from Zhenhong/next a9a863d Merge remote-tracking branch 'upstream/next' into next db29e29 update Makefile to fix missing LD_LIBRARY_PATH in hw issue(CR-1128335) a311d95 Merge pull request Xilinx#317 from shengl/next-tutorial a3cb814 Merge pull request Xilinx#330 from shengl/next-fix-CR-1127528 b1a5fe2 Update demo_start.py 07c8b6e Update demo_start.py ffdff1e fix golden value check ae2248e � 8ff83eb Fix u50build crs (Xilinx#329) b648d94 fix hw build and host error (Xilinx#328) be919b6 fix error in gradient calculation (Xilinx#327) e0f566a Merge pull request Xilinx#323 from shengl/next-revert 70f5d4f Merge pull request Xilinx#325 from shengl/next-fix-CR-1127528 48dca5d Merge pull request Xilinx#321 from sibow/next 5273d05 fix cr ef1cd05 add explaination for number of csv parser d632218 revert utils.mk edb864e Merge pull request Xilinx#322 from Zhenhong/next 95bd3e7 knn documentations 2394aef add description for template parameter api.json 023f27c Merge pull request Xilinx#320 from Zhenhong/next 91508cd Merge pull request Xilinx#316 from shengl/next-strtree-doc 0a310c8 fix typo error in api description 64749d3 Merge pull request Xilinx#319 from shengl/next-revert 17c11ee Merge pull request Xilinx#318 from Zhenhong/next 4a3b507 not support auto update Makefile, fix CR-1127263 45ef55d revert Makefile (cannot auto update) 6ba3c88 clang_format b616e26 Merge remote-tracking branch 'upstream/next' into next c201b4c remove etl info 669e7d3 add strtree doc d615946 clarify the csv scanner kernel 33bdfd2 Merge pull request Xilinx#314 from yuanqian/update 809422e Merge pull request Xilinx#309 from shengl/next-tutorial 7501cf3 fix spell errors 3971884 update tutorial.rst ef4521d update Makefile 46a4e0a Merge pull request Xilinx#313 from tuol/fix_cr_1122544 f2da6d5 update tutorial.rst 471d729 update connectivity 1cf1121 update connectivity 85e3273 Merge pull request Xilinx#312 from leol/fix-seg-fault 2cfe7e8 Fix seg-fault issue in regex (L3 SC) 6ed24d7 Merge pull request Xilinx#311 from yuanqian/next 528502f Merge pull request Xilinx#310 from shengl/next-fix-cr-22p1 e7900ac update description and Makefile f81cde6 Fix bugs caused by changes in u250 resource distribution 570869a remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 c9ce4cb Merge remote-tracking branch 'upstream/next' into next c4f681d Revert "remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831" 205d4ba remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 80828e7 fix cr, not meet timing 1e6c956 add tutorial.rst for library 9d16cfd replace cflags with clflags (Xilinx#308) f9271b9 Merge pull request Xilinx#278 from shengl/next-geospatial 2bdf9bf update Makefile b87a182 move swig & arrow build file to ext folder b2eb439 Merge pull request Xilinx#306 from Zhenhong/next 0b2fad4 fix CR-1122218 8417203 conv fix (Xilinx#305) a583923 Merge pull request Xilinx#304 from Zhenhong/next fdeaea8 decrease clock frequency from 300MHz to 250MHz 23fab12 fix design not meet timing issue CR-1123916 f9dc2c9 reduce instance to fix partially-conflicted nets issue CR-1123132 94957b6 modify size ca88eab Merge pull request Xilinx#301 from liyuanz/add_time 343bb50 modfiy description.json ded4f92 add dat folder a5a06ba adjust file location 16eb6fc remove cmake install f0799d7 Merge pull request Xilinx#302 from sibow/next 5bc5688 fix code bug 53d611d free buffer 92c937f fix hw_emu bug 5035336 fix hw_emu build bug 736cba4 multithread execute data preparation and kernel computation 8b38898 re-run bd029af add time 96cfe05 Merge branch 'next' into next-geospatial bb391ad add database to Jenkinsfile 697e10a change to load-balance; fix 4/8 pu hang issue. 249622a fix swig install bug in jks 1338bc1 add namespace ce27c16 test jks env 4a31247 test jks 0c6f5ba test jks env e4c8f84 update 154dae3 update env e23ad93 install swig c36c578 update 60e69e7 optimize gcc 0e7170a Merge pull request Xilinx#299 from sibow/next 48eaddb Merge pull request Xilinx#300 from liyuanz/increase cf41987 Merge pull request Xilinx#295 from leol/fix-CR-1122134 224cb86 add geospatial case with supporting system compiler 1cca005 update cmodel case 977f483 increase time cf95f3c support index in kernel 177d7d2 fix bug in handling '\n' 18e5404 switch python e0b2afb replace whiltelist/blacklist to allowlist/blocklist (Xilinx#298) 25e9717 add memory/time for mem/time limit cases (Xilinx#297) 4c5d118 add memory (Xilinx#296) 52ca339 Fix for linking error found in daily regression 29a7c28 Merge pull request Xilinx#289 from sibow/next 5437f3d split file into blocks 8317d90 add support for u2 ff354b8 rm L1 implementations a04014e Merge branch 'next' of gitenterprise.xilinx.com:FaaSApps/xf_DataAnalytics into next ecebfb6 add L2 kernel, change platform setting 813d32b Merge pull request Xilinx#293 from changg/fix_scs fbec276 Merge pull request Xilinx#291 from leol/smartssd-m1 0349d34 increase time (Xilinx#292) 0409239 update L1 input point 57cefc7 Switch ref-code from master to next as they are the same 02a90ba change graph branch bd9f735 update L1 case include path 7c6dfd8 update upstream dependency 0183f2b clang format 51e2354 Merge branch 'knn_dev' into next Add knn L1/L2 apis 1ec4da8 change test data 6d344a8 add test data 3632375 change preprocess mode 9b36766 sort ascending 4d11300 Fix the csim/cosim mismatch as uninitilized mem (Xilinx#287) 5f746c7 fix makefiles 96a0ea2 fix --sp tag issue for Gradient_Boosted_Tree_Regression (Xilinx#288) cd3ba53 2pu hw validated e3c2c5d Merge pull request Xilinx#281 from leol/smartssd-m1 289b241 update Makefile and utils.mk (Xilinx#284) 7dced4c Update upstream dependencies in Jenkinsfile for using xf_compression/xf_security primitives 259e131 Rename files + add namespace 8bce1c5 Re-org/add namespace/polishing for L3 Gunzip + CSV c6ea1b7 update targes (Xilinx#285) 0ae7da4 pass hls cosim; pass sw_emu 014fc78 Revise Copyright for df_utils.hpp in L1 99dc30f Split CSV parser of Samsung PoC Alpha as overloaded primitive to L1 064bff9 cosim pass: add array size, stream depth and flp 518b0c3 Remove redundant C_MODEL flow files + Add comments 2ba5f61 Copyright for all files ralated to Gunzip+CSV e40f678 Regression test settings for gunzip+csv 2df3733 Clang format for both 3.9.0 and 8.0.0 7ca6cbd Regenerate Makefile using updated sc-makefile-gen dc8ce36 draft metadata files (Xilinx#282) bc859ff Remove C & OCL flows in Gunzip+CSV 5da5a7a Clang format Gunzip+CSV kernel files 3f08666 Clang format Gunzip+CSV related files 4681ffa Fix the open file out-of-bound issue in Gunzip+CSV 41ce5bf Add Q6 test to host 9dda3d3 Gunzip+CSV parser from SmartSSD M1 537063e add index in schema, avoid output out-of-order issue. 8e5f0f6 add distance and insert top k 7712df1 csv parser with demo data; csim pass 969e42d Merge pull request Xilinx#279 from changg/aws-support 389ece4 fix parquet write 33faf31 aws support 7734c35 standardization e5cce67 update Makefile de9ef99 add python 1ca474c gcc path 0dd03ab gcc cafaa4e update arrow_env.sh 2a21f10 Specify g++ version 56c2045 update Makefile 558e50a update Makefile 3233b2c update Makefie 83489d9 fix json bug a6986e1 fix json bug 8a3037f modify Makefile d716c73 add test date b16d689 optimize contains_test ccfac42 add first version of contains 43e86fb Add fix for CR-1115640 (Xilinx#272) 84d8b26 Merge pull request Xilinx#271 from xingw/json_parser 97aa786 change 2021.2_stable_latest to 2022.1_stable_latest 15998a2 Code clean b1c61a3 Clean the code ddb8329 Cosim passed with 2/4/8 PU setting 9897a93 Correct the pragma 00463f1 Add json parser API, CSIM passed 415f4fc Clean the unused structs a99edd0 add benchmark in subpage after move benchmark.rst to parent dir 242a872 fix https://jira.xilinx.com/browse/CR-1101226 af4255a Merge remote-tracking branch 'upstream/next' into next sync 3bcc4ef Merge remote-tracking branch 'upstream/next' into next sync 859bdfd Merge remote-tracking branch 'upstream/next' into next sync 70f0997 Merge pull request #1 from yuanqian/benchmark_1 a359309 fix conflict ef5761e Merge pull request Xilinx#19 from tuol/next 2a306c9 update Jenkinsfile and description.json 2a6c4a4 Merge pull request Xilinx#15 from tuol/next Co-authored-by: sdausr <sdausr@xilinx.com>
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10685b8 Merge pull request Xilinx#323 from yunleiz/next 52e4ed0 [license] add SPDX-License-Identifier: X11 dad0121 [license] add SPDX-License-Identifier: X11 f793fde Merge pull request Xilinx#322 from congt/next 040bd2c [coding style] caec7f9 [foc-sensorless]change rated current to stall current 745bc2a Merge pull request Xilinx#321 from yunleiz/next 972c283 [sensor] change rated current to stall current 3ff8839 [refine] refine comment 6325d38 Merge pull request Xilinx#320 from yunleiz/next d2c5819 [foc] add two pics 36106e7 Merge pull request Xilinx#319 from yuanjieh/readme-license 5c8b317 Update top readme for license change and remove empty sections temporally 617bc83 Merge pull request Xilinx#318 from yunleiz/next 74bc468 [refine] clean codes 207fdd8 Merge pull request Xilinx#317 from yunleiz/next 4587527 [format] for smo aeff12e [refine] testcase a878fde [clang] format files 046e73b [refine] refine some unused codes 3a0fac0 [refine] remove unused files dd143a4 Merge pull request Xilinx#316 from yunleiz/next 5ceeb86 [makefile] get back 12bb5f9 Merge pull request Xilinx#315 from yunleiz/next e9084dd [format] format file ed0f03d [format] 95e9cb0 [format] all files c1ab04c [license] change to MITx11 54dbffc [license] change to MITx11 a62fbd8 Merge pull request Xilinx#313 from yunleiz/next bc113fb [doc] update next release note Co-authored-by: sdausr <sdausr@xilinx.com>
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I'm currently using Vitis HLS 2022.1. Whenever my source C code contains a multiplication operation, the multipliers are created as a separate Verilog module in a new file. Is there any way to disable this behaviour? I don't mind any performance impacts due to lack of pipelining or any other optimizations.
Source C code
The multiplication is realised in a
hls_macc_mul_32s_32s_32_2_1module. I would like the multiplication to be inhls_macc.vitself.The text was updated successfully, but these errors were encountered: