"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)

[eddiehung]

From CHANGELOG:

    - Added "write_xaiger" backend
    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
    - Added "synth_xilinx -abc9" (experimental)
    - Added "synth_ice40 -abc9" (experimental)
    - Added "synth -abc9" (experimental)

[gsomlo]

I wanted to test drive this by applying it on top of current master (74945dd at the time of this writing), but trying to rebase against master failed with a merge conflict that I'm not qualified to resolve. Any chance at a rebase and force-push against master? -- Thanks!

edit: nevermind, rebasing turned out to be the wrong way to go about what I needed to do, sorry for the noise :)