GitHub - abhinavhimanshu/Real_time_Sobel_edge

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Implementation Reports system level		Implementation Reports system level
Result		Result
UART_SEND_CODE		UART_SEND_CODE
constraint		constraint
scripts		scripts
src_codes		src_codes
test_bench		test_bench
vivado_project/project_1		vivado_project/project_1
.gitattributes		.gitattributes
FDR_report.pdf		FDR_report.pdf
ReadME.txt		ReadME.txt
code_herarichy.PNG		code_herarichy.PNG

Repository files navigation

-constraint folder contains the constraint file
-Implementation Reports system level contains the system level implementaion report
-src codes contains all the source code of this projects,heriarchy of code is described in image code_heriarchy
-test_bench contains the testbench and input test vector and refrences, It also has readme file explaining the details on how to use
-UART_SEND_CODE contains the code used to send image to FPGA using UART
-vivado_project contains system level vivado synthesis and implementaiton of project
-scripts folder contains all the scripts and has readme inside explaining everything in more details.
-Result folder contains resulting images obtained from our HW architecture