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build,vendor: never carry around parts of differential signals.
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When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
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@whitequark
whitequark and Jean THOMAS committed Jul 31, 2020
1 parent c9662c5 commit d964ba9
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Showing 10 changed files with 180 additions and 160 deletions.
19 changes: 9 additions & 10 deletions nmigen/build/plat.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -148,16 +148,15 @@ def add_pin_fragment(pin, pin_fragment):
if pin.dir == "io":
add_pin_fragment(pin, self.get_input_output(pin, port, attrs, invert))

for pin, p_port, n_port, attrs, invert in self.iter_differential_pins():
for pin, port, attrs, invert in self.iter_differential_pins():
if pin.dir == "i":
add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input(pin, port, attrs, invert))
if pin.dir == "o":
add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_output(pin, port, attrs, invert))
if pin.dir == "oe":
add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_tristate(pin, port, attrs, invert))
if pin.dir == "io":
add_pin_fragment(pin,
self.get_diff_input_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))

fragment._propagate_ports(ports=self.iter_ports(), all_undef_as_ports=False)
return self.toolchain_prepare(fragment, name, **kwargs)
Expand Down Expand Up @@ -239,19 +238,19 @@ def get_input_output(self, pin, port, attrs, invert):
m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(), valid_attrs=None)

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(), valid_attrs=None)

Expand Down
16 changes: 11 additions & 5 deletions nmigen/build/res.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -128,9 +128,15 @@ def resolve(resource, dir, xdr, name, attrs):
phys_names = phys.names
port = Record([("io", len(phys))], name=name)
if isinstance(phys, DiffPairs):
phys_names = phys.p.names + phys.n.names
port = Record([("p", len(phys)),
("n", len(phys))], name=name)
phys_names = []
record_fields = []
if not self.should_skip_port_component(None, attrs, "p"):
phys_names += phys.p.names
record_fields.append(("p", len(phys)))
if not self.should_skip_port_component(None, attrs, "n"):
phys_names += phys.n.names
record_fields.append(("n", len(phys)))
port = Record(record_fields, name=name)
if dir == "-":
pin = None
else:
Expand Down Expand Up @@ -166,14 +172,14 @@ def iter_single_ended_pins(self):
if pin is None:
continue
if isinstance(res.ios[0], Pins):
yield pin, port.io, attrs, res.ios[0].invert
yield pin, port, attrs, res.ios[0].invert

def iter_differential_pins(self):
for res, pin, port, attrs in self._ports:
if pin is None:
continue
if isinstance(res.ios[0], DiffPairs):
yield pin, port.p, port.n, attrs, res.ios[0].invert
yield pin, port, attrs, res.ios[0].invert

def should_skip_port_component(self, port, attrs, component):
return False
Expand Down
47 changes: 31 additions & 16 deletions nmigen/test/test_build_res.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -85,10 +85,14 @@ def test_request_tristate(self):
self.assertEqual(ports[1].name, "i2c_0__sda__io")
self.assertEqual(ports[1].width, 1)

self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(i2c.scl, scl, {}, False),
(i2c.sda, sda, {}, False),
])
scl_info, sda_info = self.cm.iter_single_ended_pins()
self.assertIs(scl_info[0], i2c.scl)
self.assertIs(scl_info[1].io, scl)
self.assertEqual(scl_info[2], {})
self.assertEqual(scl_info[3], False)
self.assertIs(sda_info[0], i2c.sda)
self.assertIs(sda_info[1].io, sda)

self.assertEqual(list(self.cm.iter_port_constraints()), [
("i2c_0__scl__io", ["N10"], {}),
("i2c_0__sda__io", ["N11"], {})
Expand All @@ -108,9 +112,13 @@ def test_request_diffpairs(self):
self.assertEqual(n.name, "clk100_0__n")
self.assertEqual(n.width, clk100.width)

self.assertEqual(list(self.cm.iter_differential_pins()), [
(clk100, p, n, {}, False),
])
clk100_info, = self.cm.iter_differential_pins()
self.assertIs(clk100_info[0], clk100)
self.assertIs(clk100_info[1].p, p)
self.assertIs(clk100_info[1].n, n)
self.assertEqual(clk100_info[2], {})
self.assertEqual(clk100_info[3], False)

self.assertEqual(list(self.cm.iter_port_constraints()), [
("clk100_0__p", ["H1"], {}),
("clk100_0__n", ["H2"], {}),
Expand All @@ -123,15 +131,22 @@ def test_request_inverted(self):
]
self.cm.add_resources(new_resources)

sig_cs = self.cm.request("cs")
sig_clk = self.cm.request("clk")
port_cs, port_clk_p, port_clk_n = self.cm.iter_ports()
self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(sig_cs, port_cs, {}, True),
])
self.assertEqual(list(self.cm.iter_differential_pins()), [
(sig_clk, port_clk_p, port_clk_n, {}, True),
])
cs = self.cm.request("cs")
clk = self.cm.request("clk")
cs_io, clk_p, clk_n = self.cm.iter_ports()

cs_info, = self.cm.iter_single_ended_pins()
self.assertIs(cs_info[0], cs)
self.assertIs(cs_info[1].io, cs_io)
self.assertEqual(cs_info[2], {})
self.assertEqual(cs_info[3], True)

clk_info, = self.cm.iter_differential_pins()
self.assertIs(clk_info[0], clk)
self.assertIs(clk_info[1].p, clk_p)
self.assertIs(clk_info[1].n, clk_n)
self.assertEqual(clk_info[2], {})
self.assertEqual(clk_info[3], True)

def test_request_raw(self):
clk50 = self.cm.request("clk50", 0, dir="-")
Expand Down
48 changes: 24 additions & 24 deletions nmigen/vendor/intel.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -248,7 +248,7 @@ def get_input(self, pin, port, attrs, invert):
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="FALSE",
i_datain=port,
i_datain=port.io,
o_dataout=self._get_ireg(m, pin, invert)
)
return m
Expand All @@ -266,7 +266,7 @@ def get_output(self, pin, port, attrs, invert):
p_use_differential_mode="FALSE",
p_use_oe="FALSE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=port,
o_dataout=port.io,
)
return m

Expand All @@ -283,7 +283,7 @@ def get_tristate(self, pin, port, attrs, invert):
p_use_differential_mode="FALSE",
p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=port,
o_dataout=port.io,
i_oe=self._get_oereg(m, pin)
)
return m
Expand All @@ -300,36 +300,36 @@ def get_input_output(self, pin, port, attrs, invert):
p_number_of_channels=pin.width,
p_use_differential_mode="FALSE",
i_datain=self._get_oreg(m, pin, invert),
io_dataio=port,
io_dataio=port.io,
o_dataout=self._get_ireg(m, pin, invert),
i_oe=self._get_oereg(m, pin),
)
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_in",
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="TRUE",
i_datain=p_port,
i_datain_b=n_port,
i_datain=port.p,
i_datain_b=port.n,
o_dataout=self._get_ireg(m, pin, invert)
)
return m

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_out",
Expand All @@ -338,17 +338,17 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
p_use_differential_mode="TRUE",
p_use_oe="FALSE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=p_port,
o_dataout_b=n_port,
o_dataout=port.p,
o_dataout_b=port.n,
)
return m

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_out",
Expand All @@ -357,27 +357,27 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
p_use_differential_mode="TRUE",
p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert),
o_dataout=p_port,
o_dataout_b=n_port,
o_dataout=port.p,
o_dataout_b=port.n,
i_oe=self._get_oereg(m, pin),
)
return m

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
if pin.xdr == 1:
p_port.attrs["useioff"] = 1
n_port.attrs["useioff"] = 1
port.p.attrs["useioff"] = 1
port.n.attrs["useioff"] = 1

m = Module()
m.submodules[pin.name] = Instance("altiobuf_bidir",
p_enable_bus_hold="FALSE",
p_number_of_channels=pin.width,
p_use_differential_mode="TRUE",
i_datain=self._get_oreg(m, pin, invert),
io_dataio=p_port,
io_dataio_b=n_port,
io_dataio=port.p,
io_dataio_b=port.n,
o_dataout=self._get_ireg(m, pin, invert),
i_oe=self._get_oereg(m, pin),
)
Expand Down
40 changes: 20 additions & 20 deletions nmigen/vendor/lattice_ecp5.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -553,9 +553,9 @@ def get_input(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=port[bit],
i_I=port.io[bit],
o_O=i[bit]
)
return m
Expand All @@ -565,10 +565,10 @@ def get_output(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=port[bit]
o_O=port.io[bit]
)
return m

Expand All @@ -577,11 +577,11 @@ def get_tristate(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port[bit]
o_O=port.io[bit]
)
return m

Expand All @@ -590,63 +590,63 @@ def get_input_output(self, pin, port, attrs, invert):
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(len(port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_B=port[bit]
io_B=port.io[bit]
)
return m

def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=p_port[bit],
i_I=port.p[bit],
o_O=i[bit]
)
return m

def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=p_port[bit],
o_O=port.p[bit],
)
return m

def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=p_port[bit],
o_O=port.p[bit],
)
return m

def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(len(p_port)):
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_B=p_port[bit],
io_B=port.p[bit],
)
return m

Expand Down
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