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Negative side of diff pair is exposed on ECP5 #456

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jeanthom opened this issue Jul 31, 2020 · 0 comments · Fixed by #459
Closed

Negative side of diff pair is exposed on ECP5 #456

jeanthom opened this issue Jul 31, 2020 · 0 comments · Fixed by #459

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@jeanthom
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@jeanthom jeanthom commented Jul 31, 2020

Code example:

from nmigen import *
from nmigen_boards.ecpix5 import ECPIX585Platform

class Top(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        ddr3 = platform.request("ddr3", 0, dir={"dqs":"-"})
        m.submodules += [
        	Instance("BB",
				i_I=1,
				i_T=1,
				o_O=Signal(),
				io_B=ddr3.dqs.n[0])
        ]

        return m

if __name__ == "__main__":
    ECPIX585Platform().build(Top(), do_program=True)

Console output:

ERROR: IO 'ddr3_0__dqs__n[0]' is unconstrained in LPF (override this error with --lpf-allow-unconstrained)
0 warnings, 1 error
Traceback (most recent call last):
  File "diffpairissue.py", line 20, in <module>
    ECPIX585Platform().build(Top(), do_program=True)
  File "/home/jeanthomas/Documents/nmigen/nmigen/build/plat.py", line 94, in build
    products = plan.execute_local(build_dir)
  File "/home/jeanthomas/Documents/nmigen/nmigen/build/run.py", line 95, in execute_local
    subprocess.check_call(["sh", "{}.sh".format(self.script)])
  File "/usr/lib64/python3.8/subprocess.py", line 364, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sh', 'build_top.sh']' returned non-zero exit status 255.
@jeanthom jeanthom changed the title Cannot get raw IOs from a diff pair group Negative side of diff pair is exposed on ECP5 Jul 31, 2020
@whitequark whitequark added the bug label Jul 31, 2020
@whitequark whitequark added this to the 0.3 milestone Jul 31, 2020
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
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