Memory ReadPort and WritePort are broken for negedge clockdomains #611
Description
Currently, ReadPort and WritePort do not respect the clock polarity of the domain. This makes it impossible to use Memory with negedge domains.
see:
https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L281 https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L177