Util axis fifo asym #1287
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Util axis fifo asym #1287
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Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
- Fixed a bug where datapaths with different widths caused data corruption - Added an option to manually restrict certain parameter values based on the datapath widths Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
- Added additional perspective option for the address - Updated the IPs that are affected Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
- Rounded up the almost empty and full threshold values - Fixed the tlast signal on the master side Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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PR Description
Added initialization for ad_mem, which helps the testbench by automatically clearing all the FIFOs at the beginning of the simulation.
Fixed a bug that was related to different data width on the input and output of the FIFO, when it was using asymmetric clocks.
Added parameter to be able to set the FIFO size from the perspective of Master or Slave.
Added parameter to toggle to result in a reduced size FIFO.
Update the affected Data Offload IP.
Tested all of the changes in the Testbenches repository, where these IPs were used, the tests pass.
analogdevicesinc/testbenches#77
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