[RFC] SOF build on arbitrary architectures

samples/audio/sof/CMakeLists.txt

@@ -6,25 +6,27 @@ set(sof_module $ENV{ZEPHYR_BASE}/../modules/audio/sof)
 
 # This needs to be before find_package, see
 # https://github.com/zephyrproject-rtos/zephyr/issues/24512
-set(sof_defconfigs ${sof_module}/src/arch/xtensa/configs)
+set(sof_defconfigs ${sof_module}/src/arch)
 if (${BOARD} STREQUAL up_squared_adsp)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/apollolake_defconfig)
-endif()
-if (${BOARD} STREQUAL intel_adsp_cavs18)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/cannonlake_defconfig)
-endif()
-if (${BOARD} STREQUAL intel_adsp_cavs20)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/icelake_defconfig)
-endif()
-if (${BOARD} STREQUAL intel_adsp_cavs25)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/tigerlake_defconfig)
-endif()
-if (${BOARD} STREQUAL intel_adsp_baytrail)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/baytrail_defconfig)
-endif()
-if (${BOARD} STREQUAL intel_adsp_broadwell)
-  set(OVERLAY_CONFIG ${sof_defconfigs}/broadwell_defconfig)
-endif()
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/apollolake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs18)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/cannonlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs20)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/icelake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs25)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/tigerlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_baytrail)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/baytrail_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_broadwell)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/broadwell_defconfig)
+else ()
+  set(OVERLAY_CONFIG ${sof_defconfigs}/host/configs/library_defconfig)
+  set(ARCH host)
+endif ()
+
+if (NOT DEFINED ARCH)
+  set(ARCH xtensa)
+endif ()
 
 find_package(Zephyr HINTS $ENV{ZEPHYR_BASE})
 project(sample_sof)
@@ -36,6 +38,6 @@ target_sources(app PRIVATE
 zephyr_interface_library_named(sof_lib)
 
 zephyr_library_include_directories(app PUBLIC
-    ${sof_module}/src/arch/xtensa/include
+    ${sof_module}/src/arch/${ARCH}/include
     ${sof_module}/src/include
   )

samples/audio/sof/prj.conf

@@ -2,3 +2,4 @@ CONFIG_SOF=y
 CONFIG_SMP=n
 CONFIG_LOG=y
 CONFIG_MP_NUM_CPUS=1
+CONFIG_BUILD_OUTPUT_BIN=n

scripts/west_commands/sign.py

@@ -420,19 +420,34 @@ def sign(self, command, build_dir, bcfg, formats):
         board = cache['CACHED_BOARD']
         log.inf('Signing for board ' + board)
         target = self.edt_get_rimage_target(board)
-        log.inf('Signing for SOC target ' + target)
+        conf = target + '.toml'
+        log.inf('Signing for SOC target ' + target + ' using ' + conf)
 
         if not args.quiet:
             log.inf('Signing with tool {}'.format(tool_path))
 
+        s = pathlib.Path(os.environ.get('ZEPHYR_BASE'))
+
         bootloader = str(b / 'zephyr' / 'bootloader.elf.mod')
         kernel = str(b / 'zephyr' / 'zephyr.elf.mod')
         out_bin = str(b / 'zephyr' / 'zephyr.ri')
+        out_xman = str(b / 'zephyr' / 'zephyr.ri.xman')
+        out_tmp = str(b / 'zephyr' / 'zephyr.rix')
+        conf_path = str(s / '..' / 'modules' / 'audio' / 'sof' / 'rimage' / 'config' / conf)
 
         sign_base = ([tool_path] + args.tool_args +
-                     ['-o', out_bin, '-m', target, '-i', '3'] +
+                     ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] +
                      [bootloader, kernel])
 
         if not args.quiet:
             log.inf(quote_sh_list(sign_base))
         subprocess.check_call(sign_base)
+
+        filenames = [out_xman, out_bin]
+        with open(out_tmp, 'wb') as outfile:
+            for fname in filenames:
+                with open(fname, 'rb') as infile:
+                    outfile.write(infile.read())
+
+        os.remove(out_bin)
+        os.rename(out_tmp, out_bin)

soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h

@@ -142,6 +142,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000

soc/xtensa/intel_adsp/cavs_v15/linker.ld

@@ -132,6 +132,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -161,6 +164,7 @@ PHDRS
   ucram_phdr PT_LOAD;
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
 _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -567,4 +576,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h

@@ -139,6 +139,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000

soc/xtensa/intel_adsp/cavs_v18/linker.ld

@@ -112,6 +112,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -141,6 +144,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
 #endif
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -532,4 +541,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h

@@ -139,6 +139,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000

soc/xtensa/intel_adsp/cavs_v20/linker.ld

@@ -112,8 +112,15 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 PHDRS
 {
   vector_memory_lit_phdr PT_LOAD;
@@ -141,6 +148,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -532,4 +540,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h

@@ -139,6 +139,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000

soc/xtensa/intel_adsp/cavs_v25/linker.ld

@@ -112,6 +112,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 
   lpsram_alt_reset_vec_seg :
         org = LP_SRAM_ALT_RESET_VEC_BASE,
@@ -154,6 +157,7 @@ PHDRS
 
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 
   lpsram_mem_phdr PT_LOAD;
   sram_alt_fw_reset_vec_phdr PT_LOAD;
@@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;
 #endif
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -600,4 +609,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/common/CMakeLists.txt

@@ -27,7 +27,5 @@ if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR
    CONFIG_SOC_SERIES_INTEL_CAVS_V25)
-	zephyr_library_sources(soc.c)
-	zephyr_library_sources(soc_mp.c)
 	include(bootloader.cmake)
 endif()

soc/xtensa/intel_adsp/common/adsp.c

@@ -12,44 +12,3 @@
 
 #include <logging/log.h>
 LOG_MODULE_REGISTER(sof);
-
-#include <ipc.h>
-#include <soc/shim.h>
-#include <adsp/io.h>
-
-#include <cavs/mailbox.h>
-
-/*
- * Sets up the host windows so that the host can see the memory
- * content on the DSP SRAM.
- */
-static void prepare_host_windows(void)
-{
-	/* window0, for fw status */
-	sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
-	sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
-		    DMWBA(0));
-	memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
-	      HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-	SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
-			 HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-
-	/* window3, for trace
-	 * zeroed by trace initialization
-	 */
-	sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
-	sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
-		    DMWBA(3));
-	memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
-	SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
-}
-
-static int adsp_init(const struct device *dev)
-{
-	prepare_host_windows();
-
-	return 0;
-}
-
-/* Init after IPM initialization and before logging (uses memory windows) */
-SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);