Source explained

It start all with the makefile in make directory:

https://github.com/angerangel/r3bazaar/blob/master/make/makefile

The makefile is the main file to build rebol, you may launch it in many ways (aka make targets):

• make clean
• make top
• make update
• make make
• make all (to build rebol and more...)
• make view (to build rebol)
• make prep
• make prep-lib
• make prep-core
• make prep-view
• make prep-encap-view
• make prep-encap-boot-view
• make prep-encap-core
• make prep-encap-boot-core
• make purge
• make test
• make install
• make build
• make cln
• make check

Brief description of make utility

The make utility is used to describe what to do in order to build something, the thing to build may be almost anything (a book, a text, a song...) but usually it is a software program.

Make uses the same concept as recipes in a cooking book so let's use this analogy as example to describe it. In a cooking book you have different kinds of food listed in book pages, when you select the page of one kind of food you get the ingredients needed to make that food and a list of tasks or steps to make the food using the ingredients, you can say that the selected food depends on the ingredients because if you haven't got the ingredients you cannot make the food and if you change the ingredients you change somehow the food. An example of recipe may be:

Simple Salad

Ingredients: lettuce, tomato, oil, salt

1. cut the lettuce and tomato in small pieces
2. melt it all with oil and salt

Let's write the same recipe using make syntax:

simple-salad: lettuce tomato oil salt
   cut lettuce
   cut tomato
   melt all
   add salt oil

As you can see both syntax are pretty the same, the general syntax for make is:

target: prerequisities
   recipe

where target is the thing you want to build, prerequisities are zero or more things target depends on (ingredients) separated by spaces and recipe is a list of tasks each one in a line describing what to do in order to get the target. In order to build a target you must first build all its prerequisities. A target is built only if some of its prerequisities change.

A make file (known as makefile) is simply a list of targets to build. You can also find variables in a makefile, variables is just special names you define once and use in several places, variables are defined using an equal sign (this way: variable-name=variable-value) and then you use the variable simply prefixing its name in parenthesis with a dollar sign ( $(variable-name) ) to get its value. You can define variables everywhere in the makefile and you can use it from the place you define it.