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phy: lpddr5: Align CA to start before posedge of CK_T #937

phy: lpddr5: Align CA to start before posedge of CK_T

phy: lpddr5: Align CA to start before posedge of CK_T #937

Workflow file for this run

name: ci
on: [push, pull_request]
env:
LITEX_BRANCH: antmicro/ddr5-support
jobs:
build:
runs-on: ubuntu-22.04
strategy:
fail-fast: false
matrix:
pytest_args:
- 'test -k "not (Verilator or ddr5)"'
- 'test/test_lpddr4.py -k "Verilator"'
- 'test/test_lpddr5.py -k "Verilator"'
steps:
# Checkout Repository
- name: Checkout
uses: actions/checkout@v3
- name: Setup CCache
uses: hendrikmuhs/ccache-action@v1.2
# Install Tools
- name: Install Tools
run: |
sudo apt-get update
sudo apt-get install wget build-essential python3 ninja-build -y
sudo apt-get install libevent-dev libjson-c-dev flex bison git -y
sudo apt-get install libfl-dev libfl2 zlib1g-dev python3-pip autoconf -y
pip3 install setuptools
pip3 install requests
pip3 install pexpect
pip3 install meson==0.62.0
pip3 install pytest==7.1.0
pip3 install numpy
- name: Install pytest-parallel
if: ${{ contains(matrix.pytest_args, 'not') }}
run: pip install pytest-parallel
# Install (n)Migen / LiteX / Cores
- name: Install LiteX
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py init install --user
# temporary hack until merged to master
git -C ../litex remote add antmicro https://github.com/antmicro/litex.git
git -C ../litex fetch antmicro
git -C ../litex checkout $LITEX_BRANCH
git -C ../litex-boards checkout 6c05ddae1ba4d2b363e80001919e4682745cc3cf
# Install RISC-V GCC
- name: Install RISC-V GCC
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
# python3 litex_setup.py gcc
curl -L https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.08/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14.tar.gz | tar -xzf -
mv riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14 ../riscv64-unknown-elf-gcc
sudo mkdir /usr/local/riscv
sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv
# Build / Install Verilator
- name: Build Verilator
if: ${{ !contains(matrix.pytest_args, 'not') }}
run: |
sudo apt install help2man
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
git clone https://github.com/verilator/verilator
cd verilator
autoconf
./configure
make -j$(nproc)
sudo make install
# Install Project
- name: Install Project
run: python3 setup.py develop --user
# Test
- name: Run Tests
if: ${{ contains(matrix.pytest_args, 'not') }}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest ${{ matrix.pytest_args }} --verbose --workers auto
- name: Run Tests
if: ${{ !contains(matrix.pytest_args, 'not') }}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest ${{ matrix.pytest_args }} --verbose
test_ddr5:
runs-on: ubuntu-22.04
name: "DDR5 tests"
strategy:
fail-fast: false
matrix:
pytest_args:
- 'test/test_ddr5_phy.py'
- 'test/test_ddr5_rcd_core.py'
- 'test/test_ddr5_rcd_decoder.py'
- 'test/test_ddr5_rcd_actor_mrw.py'
- 'test/test_ddr5_rcd_sideband.py'
- 'test/test_ddr5_rdimm_regression.py'
- 'test/test_ddr5_rdimm_phy.py'
steps:
# Checkout Repository
- name: Checkout
uses: actions/checkout@v3
- name: Setup CCache
uses: hendrikmuhs/ccache-action@v1.2
# Install Tools
- name: Install Tools
run: |
sudo apt-get update
sudo apt-get install wget build-essential python3 ninja-build -y
sudo apt-get install libevent-dev libjson-c-dev flex bison git -y
sudo apt-get install libfl-dev libfl2 zlib1g-dev python3-pip autoconf -y
pip3 install setuptools
pip3 install requests
pip3 install pexpect
pip3 install meson==0.62.0
pip3 install pytest==7.1.0
pip3 install numpy
- name: Install pytest-parallel
run: pip install pytest-parallel
# Install (n)Migen / LiteX / Cores
- name: Install LiteX
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py init install --user
# temporary hack until merged to master
git -C ../litex remote add antmicro https://github.com/antmicro/litex.git
git -C ../litex fetch antmicro
git -C ../litex checkout $LITEX_BRANCH
git -C ../litex-boards checkout 6c05ddae1ba4d2b363e80001919e4682745cc3cf
# Install RISC-V GCC
- name: Install RISC-V GCC
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
# python3 litex_setup.py gcc
curl -L https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.08/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14.tar.gz | tar -xzf -
mv riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14 ../riscv64-unknown-elf-gcc
sudo mkdir /usr/local/riscv
sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv
# Install Project
- name: Install Project
run: python3 setup.py develop --user
- name: Run Tests
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest ${{ matrix.pytest_args }} --verbose --workers auto
test_ddr5_verilator:
runs-on: ubuntu-22.04
name: "DDR5 Verilator tests"
strategy:
fail-fast: false
matrix:
with_sub_channels:
- "true"
- "false"
dq_dqs_ratio:
- "4"
- "8"
module_in_rank:
- "1"
- "2"
include:
- with_sub_channels: "true"
rcd_mode: "pass_through"
- with_sub_channels: "true"
rcd_mode: "normal"
- dq_dqs_ratio: "8"
with_dm: "true"
- dq_dqs_ratio: "8"
with_dm: "false"
steps:
# Checkout Repository
- name: Checkout
uses: actions/checkout@v2
- name: Setup CCache
uses: hendrikmuhs/ccache-action@v1
# Install Tools
- name: Install Tools
run: |
sudo apt-get update
sudo apt-get install wget build-essential python3 ninja-build -y
sudo apt-get install libevent-dev libjson-c-dev flex bison git -y
sudo apt-get install libfl-dev libfl2 zlib1g-dev python3-pip autoconf -y
pip3 install setuptools
pip3 install requests
pip3 install pexpect
pip3 install meson==0.62.0
pip3 install pytest==7.1.0
# Install (n)Migen / LiteX / Cores
- name: Install LiteX
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py init install --user
# temporary hack until merged to master
git -C ../litex remote add antmicro https://github.com/antmicro/litex.git
git -C ../litex fetch antmicro
git -C ../litex checkout $LITEX_BRANCH
git -C ../litex-boards checkout 6c05ddae1ba4d2b363e80001919e4682745cc3cf
# Install RISC-V GCC
- name: Install RISC-V GCC
run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
# python3 litex_setup.py gcc
curl -L https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.08/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14.tar.gz | tar -xzf -
mv riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14 ../riscv64-unknown-elf-gcc
sudo mkdir /usr/local/riscv
sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv
- name: Build Verilator
run: |
sudo apt install help2man
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
git clone https://github.com/verilator/verilator
cd verilator
autoconf
./configure
make -j$(nproc)
sudo make install
# Install Project
- name: Install Project
run: python3 setup.py develop --user
# RCD regression test
- name: Run Tests
if: ${{ matrix.rcd_mode == 'pass_through'}}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest test/test_ddr5_rdimm_regression.py -k ${{ format('test_ddr5_rcd_reg_sim_dq_dqs_ratio_{0}_modules_per_rank_{1}', matrix.dq_dqs_ratio, matrix.module_in_rank) }} --verbose
# RCD test
- name: Run Tests
if: ${{ matrix.rcd_mode == 'normal'}}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest test/test_ddr5_rdimm.py -k ${{ format('test_ddr5_rcd_sim_dq_dqs_ratio_{0}_modules_per_rank_{1}', matrix.dq_dqs_ratio, matrix.module_in_rank) }} --verbose
# NO RCD test
- name: Run Tests
if: ${{ matrix.rcd_mode != 'pass_through' && matrix.rcd_mode != 'normal' && matrix.dq_dqs_ratio != '8' }}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest test/test_ddr5.py -k ${{ format('test_ddr5_sim_dq_dqs_ratio_4_with_sub_channels_{0}_modules_per_rank_{1}', matrix.with_sub_channels, matrix.module_in_rank) }} --verbose
if: ${{ matrix.rcd_mode != 'pass_through' && matrix.rcd_mode != 'normal' && matrix.dq_dqs_ratio == '8' && matrix.with_dm }}

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run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest test/test_ddr5.py -k ${{ format('test_ddr5_sim_dq_dqs_ratio_8_with_sub_channels_{0}_modules_per_rank_{1}_with_dm', matrix.with_sub_channels, matrix.module_in_rank) }} --verbose
if: ${{ matrix.rcd_mode != 'pass_through' && matrix.rcd_mode != 'normal' && matrix.dq_dqs_ratio == '8' && !matrix.with_dm }}
run: |
export PATH=/usr/local/riscv/bin:$PATH
pytest test/test_ddr5.py -k ${{ format('test_ddr5_sim_dq_dqs_ratio_8_with_sub_channels_{0}_modules_per_rank_{1}_without_dm', matrix.with_sub_channels, matrix.module_in_rank) }} --verbose