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DDR5: Improve timing in S7CRG #939

DDR5: Improve timing in S7CRG

DDR5: Improve timing in S7CRG #939

Triggered via push March 27, 2024 08:55
Status Startup failure
Total duration
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ci.yml

on: push
Matrix: build
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Matrix: DDR5 tests
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Matrix: DDR5 Verilator tests
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1 error
Invalid workflow file: .github/workflows/ci.yml#L268
The workflow is not valid. .github/workflows/ci.yml (Line: 268, Col: 9): 'if' is already defined .github/workflows/ci.yml (Line: 269, Col: 9): 'run' is already defined