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is the a way using RAM (GHDL,VHDL -> Yosys) FPGA (onchip) blockRAM 521 words 16 bit as ROM ?
In Lattice ICE40 FPGA RAM could be preloaded during FPGA power on.
Hoping to receive some examples or advice, I meanwhile remain,
Patrick Pelgrims
The text was updated successfully, but these errors were encountered:
Dear,
is the a way using RAM (GHDL,VHDL -> Yosys) FPGA (onchip) blockRAM 521 words 16 bit as ROM ?
In Lattice ICE40 FPGA RAM could be preloaded during FPGA power on.
Hoping to receive some examples or advice, I meanwhile remain,
Patrick Pelgrims
The text was updated successfully, but these errors were encountered: