GitHub - bjybs123/Pipelined-RV32I: Verilog Implementation of 5-stage pipelined RISC-V RV32I Instruction Set Architecture

bjybs123 / Pipelined-RV32I Public

Verilog Implementation of 5-stage pipelined RISC-V RV32I Instruction Set Architecture

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
Adder.v		Adder.v
BranchALU.v		BranchALU.v
ControlUnit.v		ControlUnit.v
DataMem.v		DataMem.v
EX_ForwardingUnit.v		EX_ForwardingUnit.v
EX_MEM.v		EX_MEM.v
HazardDetectionUnit.v		HazardDetectionUnit.v
ID_EX.v		ID_EX.v
ID_ForwardingUnit.v		ID_ForwardingUnit.v
IF_ID.v		IF_ID.v
ImmediateGen.v		ImmediateGen.v
InstrMem.v		InstrMem.v
MEM_WB.v		MEM_WB.v
PC.v		PC.v
RV32I.v		RV32I.v
RegisterFile.v		RegisterFile.v
WidthControl.v		WidthControl.v