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alexrprichfelker
alexrp
authored and
richfelker
committed
riscv: fix setjmp assembly when compiling for ilp32f/lp64f.
per the psABI, floating point register contents beyond the register size of the targeted ABI variant are never call-saved, so no hwcap-conditional logic is needed here and the assembly-time conditions are based purely on ABI variant macros, not the targeted ISA level.
1 parent f6944eb commit 0b86d60

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4 files changed

+72
-48
lines changed

4 files changed

+72
-48
lines changed

‎src/setjmp/riscv32/longjmp.S

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,18 +23,24 @@ longjmp:
2323
lw ra, 52(a0)
2424

2525
#ifndef __riscv_float_abi_soft
26-
fld fs0, 56(a0)
27-
fld fs1, 64(a0)
28-
fld fs2, 72(a0)
29-
fld fs3, 80(a0)
30-
fld fs4, 88(a0)
31-
fld fs5, 96(a0)
32-
fld fs6, 104(a0)
33-
fld fs7, 112(a0)
34-
fld fs8, 120(a0)
35-
fld fs9, 128(a0)
36-
fld fs10, 136(a0)
37-
fld fs11, 144(a0)
26+
#ifdef __riscv_float_abi_double
27+
#define FLX fld
28+
#else
29+
#define FLX flw
30+
#endif
31+
32+
FLX fs0, 56(a0)
33+
FLX fs1, 64(a0)
34+
FLX fs2, 72(a0)
35+
FLX fs3, 80(a0)
36+
FLX fs4, 88(a0)
37+
FLX fs5, 96(a0)
38+
FLX fs6, 104(a0)
39+
FLX fs7, 112(a0)
40+
FLX fs8, 120(a0)
41+
FLX fs9, 128(a0)
42+
FLX fs10, 136(a0)
43+
FLX fs11, 144(a0)
3844
#endif
3945

4046
seqz a0, a1

‎src/setjmp/riscv32/setjmp.S

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,18 +23,24 @@ setjmp:
2323
sw ra, 52(a0)
2424

2525
#ifndef __riscv_float_abi_soft
26-
fsd fs0, 56(a0)
27-
fsd fs1, 64(a0)
28-
fsd fs2, 72(a0)
29-
fsd fs3, 80(a0)
30-
fsd fs4, 88(a0)
31-
fsd fs5, 96(a0)
32-
fsd fs6, 104(a0)
33-
fsd fs7, 112(a0)
34-
fsd fs8, 120(a0)
35-
fsd fs9, 128(a0)
36-
fsd fs10, 136(a0)
37-
fsd fs11, 144(a0)
26+
#ifdef __riscv_float_abi_double
27+
#define FSX fsd
28+
#else
29+
#define FSX fsw
30+
#endif
31+
32+
FSX fs0, 56(a0)
33+
FSX fs1, 64(a0)
34+
FSX fs2, 72(a0)
35+
FSX fs3, 80(a0)
36+
FSX fs4, 88(a0)
37+
FSX fs5, 96(a0)
38+
FSX fs6, 104(a0)
39+
FSX fs7, 112(a0)
40+
FSX fs8, 120(a0)
41+
FSX fs9, 128(a0)
42+
FSX fs10, 136(a0)
43+
FSX fs11, 144(a0)
3844
#endif
3945

4046
li a0, 0

‎src/setjmp/riscv64/longjmp.S

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,18 +23,24 @@ longjmp:
2323
ld ra, 104(a0)
2424

2525
#ifndef __riscv_float_abi_soft
26-
fld fs0, 112(a0)
27-
fld fs1, 120(a0)
28-
fld fs2, 128(a0)
29-
fld fs3, 136(a0)
30-
fld fs4, 144(a0)
31-
fld fs5, 152(a0)
32-
fld fs6, 160(a0)
33-
fld fs7, 168(a0)
34-
fld fs8, 176(a0)
35-
fld fs9, 184(a0)
36-
fld fs10, 192(a0)
37-
fld fs11, 200(a0)
26+
#ifdef __riscv_float_abi_double
27+
#define FLX fld
28+
#else
29+
#define FLX flw
30+
#endif
31+
32+
FLX fs0, 112(a0)
33+
FLX fs1, 120(a0)
34+
FLX fs2, 128(a0)
35+
FLX fs3, 136(a0)
36+
FLX fs4, 144(a0)
37+
FLX fs5, 152(a0)
38+
FLX fs6, 160(a0)
39+
FLX fs7, 168(a0)
40+
FLX fs8, 176(a0)
41+
FLX fs9, 184(a0)
42+
FLX fs10, 192(a0)
43+
FLX fs11, 200(a0)
3844
#endif
3945

4046
seqz a0, a1

‎src/setjmp/riscv64/setjmp.S

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,18 +23,24 @@ setjmp:
2323
sd ra, 104(a0)
2424

2525
#ifndef __riscv_float_abi_soft
26-
fsd fs0, 112(a0)
27-
fsd fs1, 120(a0)
28-
fsd fs2, 128(a0)
29-
fsd fs3, 136(a0)
30-
fsd fs4, 144(a0)
31-
fsd fs5, 152(a0)
32-
fsd fs6, 160(a0)
33-
fsd fs7, 168(a0)
34-
fsd fs8, 176(a0)
35-
fsd fs9, 184(a0)
36-
fsd fs10, 192(a0)
37-
fsd fs11, 200(a0)
26+
#ifdef __riscv_float_abi_double
27+
#define FSX fsd
28+
#else
29+
#define FSX fsw
30+
#endif
31+
32+
FSX fs0, 112(a0)
33+
FSX fs1, 120(a0)
34+
FSX fs2, 128(a0)
35+
FSX fs3, 136(a0)
36+
FSX fs4, 144(a0)
37+
FSX fs5, 152(a0)
38+
FSX fs6, 160(a0)
39+
FSX fs7, 168(a0)
40+
FSX fs8, 176(a0)
41+
FSX fs9, 184(a0)
42+
FSX fs10, 192(a0)
43+
FSX fs11, 200(a0)
3844
#endif
3945

4046
li a0, 0

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