GitHub - bollu/FPGA-playground: Code written using BlueSpec Verilog, general FPGA messing around for my course

bollu / FPGA-playground Public

Code written using BlueSpec Verilog, general FPGA messing around for my course

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Name		Name	Last commit message	Last commit date
Latest commit History 76 Commits
assign1		assign1
assign2		assign2
shifter-pipelined		shifter-pipelined
.gitignore		.gitignore
Advanced-FPGA-Design-Architecture-Implementation-and-Optimization.pdf		Advanced-FPGA-Design-Architecture-Implementation-and-Optimization.pdf
Design-Recipes-for-FPGAs.pdf		Design-Recipes-for-FPGAs.pdf
bluespec-slides-detailed-pipelined-processor.pdf.crdownload		bluespec-slides-detailed-pipelined-processor.pdf.crdownload
bsv_by_example.pdf		bsv_by_example.pdf
compiling_and_Simulating_pdf.pdf		compiling_and_Simulating_pdf.pdf
reference_guide_syntax_semantics.pdf		reference_guide_syntax_semantics.pdf