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7c4b47f
enabled PLL power down and built binary
siliconwitch Oct 9, 2024
8aff612
WIP: PLL and graphics SPI registers refactor
rmetchev Oct 11, 2024
cf7089a
WIP camera/jpeg/image buffer - nothing works yet
rmetchev Oct 12, 2024
7be2218
verilator/icarus/modelism compile
rmetchev Oct 12, 2024
0dd443e
WIP
rmetchev Oct 12, 2024
d7676c6
SPI reads & writes working; PLL CSR working; PLL power up working
rmetchev Oct 18, 2024
96de982
Image buffer clock switch seems to work
rmetchev Oct 18, 2024
7cab363
update header
rmetchev Oct 18, 2024
9511f2a
update notes
rmetchev Oct 19, 2024
819a8d1
update notes
rmetchev Oct 19, 2024
13e83ef
cleanup
rmetchev Oct 19, 2024
202556e
copy from origin/raj/jpeg-optimizations branch
rmetchev Oct 19, 2024
09bcbce
Jpeg compress debug checkpoint
rmetchev Oct 19, 2024
cc206da
minor
rmetchev Oct 19, 2024
11a86da
copy from origin/raj/jpeg-optimizations branch
rmetchev Oct 19, 2024
864df9b
merge various diverged changes - WIP
rmetchev Oct 19, 2024
1139fcf
checkpoint
rmetchev Oct 19, 2024
e630b32
copy from robert/slow-jpeg-clock branch
rmetchev Oct 19, 2024
389a114
make latch blocking
rmetchev Oct 19, 2024
b627030
clean up jpeg clock
rmetchev Oct 19, 2024
7ff87a5
compression completes
rmetchev Oct 19, 2024
743acd6
cleanup
rmetchev Oct 19, 2024
eba9dad
copy from origin/raj/jpeg-optimizations branch
rmetchev Oct 20, 2024
b986bc1
copy from origin/raj/jpeg-optimizations branch
rmetchev Oct 20, 2024
f1c9f0b
camera/jpeg environment up & running
rmetchev Oct 20, 2024
4fa3b21
gamma bypass
rmetchev Oct 20, 2024
cfc7be6
clean up if to image buffer
rmetchev Oct 20, 2024
930c01e
speed up sims
rmetchev Oct 20, 2024
e6d0734
dcouple reset from PLL lock
rmetchev Oct 20, 2024
69a96c1
simulation cleanup
rmetchev Oct 20, 2024
d80e1a3
copy from origin/raj/jpeg-optimizations branch
rmetchev Oct 20, 2024
bd80cdc
minor
rmetchev Oct 23, 2024
5c23eda
add graphics SPI test
rmetchev Oct 23, 2024
758938a
add switch buffer
rmetchev Oct 23, 2024
4c92146
update
rmetchev Oct 23, 2024
5c194d9
Add files via upload
rmetchev Oct 23, 2024
40fabcd
Add files via upload
rmetchev Oct 23, 2024
ce2127a
Add files via upload
rmetchev Oct 23, 2024
26f1cd4
minor
rmetchev Oct 26, 2024
d43d8bb
PLL testbench
rmetchev Oct 27, 2024
30eb699
add assertion
rmetchev Oct 27, 2024
f74e31b
add pll ip sim for simulation reference
rmetchev Nov 7, 2024
4dd19d8
copy from camera cocotb
rmetchev Nov 7, 2024
01a5d3d
fix assertion
rmetchev Nov 7, 2024
112a22f
safe reset for DPHY power down
rmetchev Nov 7, 2024
6f881c4
copy from origin/raj/jpeg-optimizations branch
rmetchev Nov 7, 2024
a5c1a28
update header
rmetchev Nov 7, 2024
ae21795
copy from origin/raj/jpeg-optimizations branch
rmetchev Nov 7, 2024
70a5fed
spi_clock driven from Internal FPGA Fabric Entries
rmetchev Nov 7, 2024
fbb55a6
update CDC constraints for JPEG
rmetchev Nov 7, 2024
2410e92
synth update
rmetchev Nov 7, 2024
722e40c
synth update
rmetchev Nov 8, 2024
28a6b47
copy from origin/raj/jpeg-optimizations branch
rmetchev Nov 8, 2024
6785098
safe routing for SPI clock
rmetchev Nov 8, 2024
f47e4d5
minor
rmetchev Nov 8, 2024
6a84c42
power down PLL and D-PHY, read out image buffer using SPI clock
rmetchev Nov 8, 2024
99821b2
fix typos
rmetchev Nov 8, 2024
a035744
Update Camera register descriptions
rmetchev Nov 8, 2024
e014d99
Update PLL register descriptions
rmetchev Nov 8, 2024
6132d8a
simpler internal spi clock routing
rmetchev Nov 8, 2024
aed6b40
Revert "simpler internal spi clock routing"
rmetchev Nov 8, 2024
2fcf3de
fix typo
rmetchev Nov 8, 2024
83c0ae2
Cleaned up jpeg arch diagram
siliconwitch Nov 14, 2024
6b1e08c
Cleaned up FPGA doc for consistency
siliconwitch Nov 14, 2024
a358ad3
white spacing and annotation
siliconwitch Nov 14, 2024
769b86f
Switched defaults for DPHY and PLL to be on when FPGA starts
siliconwitch Nov 14, 2024
7d369f3
built binary
siliconwitch Nov 14, 2024
dfe23f9
rename
rmetchev Nov 14, 2024
c8f7a30
add graphics test
rmetchev Nov 25, 2024
6a8f5b8
usa same parameters as main
rmetchev Nov 25, 2024
4e7851a
low level jpeg test
robert-bigstream Dec 5, 2024
c925c69
power down PLL for jpeg readout
robert-bigstream Dec 5, 2024
e1d13a9
Merge branch 'main' into robert/spi-clock-refactor-0
rmetchev Dec 5, 2024
338cec6
Add 4 new QF settings: 20/30/40/80
rmetchev Dec 5, 2024
769e59f
Add 4 new QF settings: 20/30/40/80
rmetchev Dec 5, 2024
ab12c82
add comment
rmetchev Dec 6, 2024
5206572
Remove stale description
rmetchev Dec 6, 2024
cd2460d
clean up spi clock path
Dec 6, 2024
ed8d53f
Merge branch 'robert/spi-clock-refactor-0' of https://github.com/bril…
Dec 6, 2024
4d564fe
add clock gating to image buffer LRAM
rmetchev Dec 6, 2024
52f4d10
built binary
siliconwitch Dec 9, 2024
e6be7c1
Added fast camera script
siliconwitch Dec 9, 2024
0eaad7b
Added graphics tb changes
siliconwitch Dec 9, 2024
6b37f81
add graphics test
rmetchev Dec 9, 2024
9592aec
remove stale tests
rmetchev Dec 9, 2024
2e0f74b
update
rmetchev Dec 10, 2024
699ad76
re-factor graphics SPI register micro-architecture
rmetchev Dec 10, 2024
7f8b553
Merge branch 'main' into robert/spi-clock-refactor-0
rmetchev Dec 10, 2024
c77b5c4
built binary
siliconwitch Dec 10, 2024
6826b5e
update for display CDC
Dec 10, 2024
a458988
Merge branch 'robert/spi-clock-refactor-0' of https://github.com/bril…
Dec 10, 2024
b5ea4d0
balance spi clock
Dec 10, 2024
63b8d16
rebuild
Dec 10, 2024
b455a25
test for display
robert-bigstream Dec 13, 2024
e926f9e
Low-level sprite animation program
robert-bigstream Dec 14, 2024
f98a755
add buffer status register
Dec 14, 2024
143d971
rebuild
Dec 14, 2024
6ea9c70
Merge branch 'robert/spi-clock-refactor-0' of https://github.com/bril…
Dec 14, 2024
24e7dc0
add clear flag to debug status reg
rmetchev Dec 14, 2024
cc6b80a
update with updated status reg
rmetchev Dec 14, 2024
eb4b994
rebuild
Dec 14, 2024
23136fe
Add display status register
rmetchev Dec 14, 2024
a4c2f47
built binary
siliconwitch Dec 17, 2024
f7f1e38
1) New SPI command with no data 2) clean up buffer status register
rmetchev Dec 18, 2024
ace98f5
rebuild
rmetchev Dec 18, 2024
7f734ce
fix typo
rmetchev Dec 18, 2024
462b014
rebuild
rmetchev Dec 19, 2024
373c565
Merge branch 'robert/spi-clock-refactor-0' of https://github.com/bril…
rmetchev Dec 19, 2024
81f867f
Fix indentation
rmetchev Dec 19, 2024
5a7e2c7
update header
rmetchev Dec 19, 2024
f704676
SPI no-data command
robert-bigstream Dec 19, 2024
130d7fe
obsolete
robert-bigstream Dec 19, 2024
e04fc59
clean up
robert-bigstream Dec 19, 2024
f9effc9
Merge branch 'robert/spi-clock-refactor-0' of https://github.com/bril…
robert-bigstream Dec 19, 2024
60b65cb
fix addressing bug
rmetchev Dec 19, 2024
ef4f8f6
rebuild
rmetchev Dec 19, 2024
2040fe0
PLL & DPHY power down test
robert-bigstream Dec 19, 2024
ec04dd1
Updated fpga_architecture readme
siliconwitch Dec 23, 2024
7564431
reverted back to 512 fixed resolution and removed pan crop
siliconwitch Dec 23, 2024
1250afc
connected resolution input to jpeg block
siliconwitch Dec 23, 2024
af8a6d9
Adjusted camera low level test script to use 512x512 header
siliconwitch Dec 23, 2024
09c0071
built 720 resolution
siliconwitch Dec 27, 2024
72f53d9
Moved crop before debayer
siliconwitch Dec 27, 2024
474419d
built binary
siliconwitch Dec 27, 2024
6eed439
make setting of SENSOR_X_SIZE/IMAGE_X_SIZE/resolution more robust
rmetchev Dec 27, 2024
39927c4
add assertion for image resolution
rmetchev Dec 28, 2024
827265b
Sensor config working
siliconwitch Dec 30, 2024
947ad31
Merge pull request #291 from brilliantlabsAR/main
siliconwitch Jan 2, 2025
49cec98
WIP updating camera.sv to new API
siliconwitch Jan 2, 2025
995f043
Adjusted the QF tables: 15, 20, 25, 30, 35, 40, 50, 60
siliconwitch Jan 2, 2025
56a33de
update testbench simulation models for CSI
rmetchev Jan 2, 2025
9ebc536
cleanup
rmetchev Jan 2, 2025
ec25265
built binary
siliconwitch Jan 3, 2025
d1489d0
JPEG header gen almost working
siliconwitch Jan 3, 2025
2afcfed
fix QT 0x1 generation
rmetchev Jan 7, 2025
5ab8b22
Added pan feature to camera capture
siliconwitch Jan 8, 2025
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16 changes: 11 additions & 5 deletions docs/fpga-architecture.md
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,21 @@ Each function is accessed through a register. Registers are always addressed by
| 0x11 | `GRAPHICS_ASSIGN_COLOR` | Assigns a color to one of the 16 color palette slots. Color should be provided in YCbCr format.<br>**Write: `palette_index[7:0]`**<br>**Write: `y[7:0]`**<br>**Write: `cb[7:0]`**<br>**Write: `cr[7:0]`**
| 0x12 | `GRAPHICS_DRAW_SPRITE` | Draws a sprite on the screen. The first two arguments specify an absolute x and y position to print the sprite. The sprite will be printed from its top left corner. The third argument determines the width of the sprite in pixels. The fourth argument determines the number of colors contained in the sprite. This value may be 2, 4, or 16. The final argument specifies the color palette offset for assigning the color values held in the sprite against the stored colors in the palette. Following bytes will then be printed on the background frame buffer.<br>**Write: `x_position[15:0]`**<br>**Write: `y_position[15:0]`**<br>**Write: `width[15:0]`**<br>**Write: `total_colors[7:0]`**<br>**Write: `palette_offset[7:0]`**<br>**Write: `pixel_data[7:0]`**<br>**...**<br>**Write: `pixel_data[7:0]`**<br>
| 0x13 | `GRAPHICS_DRAW_VECTOR` | Draws a cubic Bézier curve from the start position to the end position. Control points 1 and 2 are relative to the start and end positions respectively, and are used to determine the shape of the curve. The final argument determines the color used from the current palette, and can be between 0 and 15.<br>**Write: `x_start_position[15:0]`**<br>**Write: `y_start_position[15:0]`**<br>**Write: `x_end_position[15:0]`**<br>**Write: `y_end_position[15:0]`**<br>**Write: `ctrl_1_x_position[15:0]`**<br>**Write: `ctrl_1_y_position[15:0]`**<br>**Write: `ctrl_2_x_position[15:0]`**<br>**Write: `ctrl_2_y_position[15:0]`**<br>**Write: `color[7:0]`**
| 0x14 | `GRAPHICS_BUFFER_SHOW` | The foreground and background buffers are switched. The new foreground buffer is continuously rendered to the display, and the background buffer can be used to load new draw commands.
| 0x14 | `GRAPHICS_BUFFER_SHOW` | The foreground and background buffers are switched. The new foreground buffer is continuously rendered to the display, and the background buffer can be used to load new draw commands.<br><br>**Note**: It is recommended to verify that the value of bit [1] of `GRAPHICS_BUFFER_STATUS` (`0x18`) is zero, in order to ensure that the previous `GRAPHICS_BUFFER_SHOW` command has been accepted before issuing a new `GRAPHICS_BUFFER_SHOW` command.
| 0x18 | `GRAPHICS_BUFFER_STATUS`| Status of graphics buffer.<br>**Read: `buffer_status[1:0]`**<br>`buffer_status[0]`: Current buffer<br>`buffer_status[1]`: Switch buffer pending
| 0x20 | `CAMERA_CAPTURE` | Starts a new image capture.
| 0x30 | `CAMERA_IMAGE_READY` | Flag indicating that the JPEG compression has been completed. It is recommended to read a 1 twice before reading the image data.<br>**Read: `image_complete[0]`**
| 0x21 | `CAMERA_BYTES_AVAILABLE`| Returns how many bytes are available to read within the capture memory.<br>**Read: `bytes_available[23:0]`**
| 0x31 | `CAMERA_BYTES_TOTAL` | Returns the size of the entropy coded segment of the JPEG data.<br>**Read: `compressed_bytes[15:0]`**
| 0x22 | `CAMERA_READ_BYTES` | Reads a number of bytes from the capture memory.<br>**Read: `data[7:0]`**<br>**...**<br>**Read: `data[7:0]`**
| 0x23 | `CAMERA_ZOOM` | Sets the zoom factor. A setting of `1` captures a 720x720 image, `2` captures 360x360, `3` captures 240x240, and `4` captures 180x180.<br>**Write: `zoom_factor[7:0]`**
| 0x24 | `CAMERA_PAN` | Pans the capture window up or down in discrete steps. A setting of `10` captures the top-most part of the image, `0` is the middle, and `-10` is the bottom-most<br>**Write: `pan_position[7:0]`**
| 0x23 | `CAMERA_RESOLUTION` | Sets the resolution of the image capture in pixels. Captured images are always square, so only one value is required.<br>**Write: `resolution[10:0]`**
| 0x25 | `CAMERA_READ_METERING` | Returns the current brightness levels for the red, green and blue channels of the camera. Two sets of values are returned representing spot and average metering.<br>**Read: `center_red_level[7:0]`**<br>**Read: `center_green_level[7:0]`**<br>**Read: `center_blue_level[7:0]`**<br>**Read: `average_red_level[7:0]`**<br>**Read: `average_green_level[7:0]`**<br>**Read: `average_blue_level[7:0]`**
| 0x26 | `CAMERA_QUALITY_FACTOR` | Sets the jpeg quality factor of the saved image. High values are higher quality but bigger size.<br>**Write: `quality_factor[1:0]`**.<br>- **0b01** = 100%<br>- **0b00** = 50%<br>- **0b11** = 25%<br>- **0b10** = 10%
| 0xDB | `GET_CHIP_ID` | Returns the chip ID value.<br>**Read: `0x81`**
| 0x26 | `CAMERA_QUALITY_FACTOR` | Sets the Quality Factor (QF) of the saved JPEG image. High values are higher quality but bigger size.<br>**Write: `quality_factor[2:0]`**<br>`0x0` = Lowest quality<br>`0x1`<br>`0x2`<br>`0x3`<br>`0x4`<br>`0x5`<br>`0x6`<br>`0x7` = Highest quality<br>
| 0x28 | `CAMERA_DPHY_POWER_DOWN`| Enables or disables the MIPI D-PHY for power saving when the camera is not needed.<br>**Write: `dphy_power_down[0]`**<br>`0x0` = Normal operation (default)<br>`0x1` = Power down
| 0x32 | `CAMERA_GAMMA_BYPASS` | Bypasses the gamma correction block when enabled. This is needed for factory camera focusing and calibration.<br>**Write: `gamma_bypass[0]`**<br>`0x0` = Normal operation (default)<br>`0x1` = Gamma correction bypassed
| 0x40 | `PLL_CONTROL` | PLL Control Register. Controls PLL power and clock mux of image buffer.<br>**Write: `pll_powerdown_n[0]`**<br>`0x00` = Power down PLL<br>`0x01` = Power on PLL (default)<br>**Write: `image_buffer_clock_sel[1]`**<br>`0x00` = Image buffer clocked from PLL generated clock (default)<br>`0x01` = Image buffer clocked from SPI clock<br>
| 0x41 | `PLL_STATUS` | Status of PLL clock outputs.<br>**Read: `pll_status[0]`**<br>`0x00` = PLL powered down or not stable yet<br>`0x01` = PLL powered on and stable
| 0xDB | `GET_CHIP_ID` | Returns the chip ID value.<br>**Read: `id_value[7:0]`**<br>`0x81` = FPGA running correctly (default)

## Graphics

Expand Down
10 changes: 5 additions & 5 deletions source/application/camera_configuration.h
Original file line number Diff line number Diff line change
Expand Up @@ -83,18 +83,18 @@ static const camera_config_t camera_config[] = {
{0x3805, 0x0b}, // Horizontal end address [7:0]
{0x3806, 0x02}, // Vertical end address [15:8]
{0x3807, 0xdb}, // Vertical end address [7:0]
{0x3808, 0x05}, // Horizontal output size [15:8]
{0x3809, 0x02}, // Horizontal output size [7:0]
{0x3808, 0x02}, // Horizontal output size [15:8]
{0x3809, 0xd4}, // Horizontal output size [7:0]
{0x380a, 0x02}, // Vertical output size [15:8]
{0x380b, 0xd2}, // Vertical output size [7:0]
{0x380c, 0x05}, // Pixels per line [15:8]
{0x380d, 0xc6}, // Pixels per line [7:0]
{0x380e, 0x03}, // Lines per frame [15:8]
{0x380f, 0x2a}, // Lines per frame [7:0]
{0x3810, 0x00}, // ISP horizontal window offset [15:8]
{0x3811, 0x00}, // ISP horizontal window offset [7:0]
{0x3810, 0x01}, // ISP horizontal window offset [15:8]
{0x3811, 0x84}, // ISP horizontal window offset [7:0]
{0x3812, 0x00}, // ISP vertical window offset [15:8]
{0x3813, 0x00}, // ISP vertical window offset [7:0]
{0x3813, 0x02}, // ISP vertical window offset [7:0]
{0x3816, 0x00}, // VSYNC start row [15:8]
{0x3817, 0x00}, // VSYNC start row [7:0]
{0x3818, 0x00}, // VSYNC end row [15:8]
Expand Down
20 changes: 0 additions & 20 deletions source/application/jpeg_header/Makefile

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1 change: 0 additions & 1 deletion source/application/jpeg_header/footer.bin

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44 changes: 0 additions & 44 deletions source/application/jpeg_header/jhdr.c

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13 changes: 0 additions & 13 deletions source/application/jpeg_header/jhdr.h

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14 changes: 0 additions & 14 deletions source/application/jpeg_header/main.c

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