Placer support for fixed placement of cells

[DallonTG]

There's no way right now to tell the placer that certain cells (i.e. top level IO) are fixed. Obviously, this means top level ports can end up getting placed where you don't actually want them for a real design.

There is a fixedPlacement variable in the PlacementGroup class so it looks like this feature has been considered. Completing this feature would be very helpful for my research (and I don't think I know the code well enough to make the best implementation of it).

[trharoldsen]

The primary issue at this point with this feature is determining the method to specify locations. Any specification method would be fine, I just need one. The cleanest method would probably be to parse the constraints files to identify placement information, but I have no interest in making a parser for this file. If you can get me an input specifying placement constraints, I can update the placer to honor them.

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On Sat, Mar 17, 2018 at 7:26 PM, Dallon ***@***.***> wrote: There's no way right now to tell the placer that certain cells (i.e. top level IO) are fixed. Obviously, this means top level ports can end up getting placed where you don't actually want them for a real design. There is a fixedPlacement variable in the PlacementGroup class so it looks like this feature has been considered. Completing this feature would be very helpful for my research (and I don't think I know the code well enough to make the best implementation of it). — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#10>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AMdCwu4qOD5CSHozYrvrRoR3F-Vo-9Bxks5tfZvBgaJpZM4SvAUx> .

[DallonTG]

Okay,

I've made an RS2 branch that parses the constraints.xdc file upon RSCP import. It is a work in progress still (no PR yet) and only handles constraints of these forms:
set_property PACKAGE_PIN M19 [get_ports sw[1]]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]

After the design has been imported, you can call design.getPortConstraintMap() to get a map from constrained port cells to sites.

Will an input like this work for you? If something else is easier, let me know. Thanks!