SAP-1 (Nexys A7-100T) — SystemVerilog + Vivado Batch Builder

This project contains a tiny SAP-1-style CPU implemented in SystemVerilog, plus Vivado TCL scripts that create a clean project, add sources and constraints, and produce a .bit file for the Nexys A7-100T (Artix-7 xc7a100tcsg324-1).
The ROM is a 16×8 image produced by the HTML assembler.

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More information / Online Assembler

Read about the project

The online assembler aids in the creation of rom files for the SAP-1 computer. It allows you to download a .zip file containing the source files and .tcl scripts to build the project.

What’s in the ZIP

src/
  sap1_top.sv
  sap1_core.sv
  rom16x8.sv
  sevenseg_hex_mux.sv
  btn_debouncer.sv
  pulse_stretcher.sv
  vga_timing_640x480_ce.sv
  vga_hex7_overlay.sv
mem/
  sap1_rom.mem                  <-- generated by the assembler
constraints/
  sap1_minimal.xdc              <-- clock-only constraints (auto-added by TCL)
  Nexys-A7-100T-Master.xdc      <-- (place your official board XDC here)
scripts/
  build_sap1_nexys_a7.tcl       <-- clean build: project -> bitstream
  rebuild_after_mem_change.tcl  <-- fast rebuild when only .mem changed

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Requirements

• Vivado (any modern version that supports Artix-7; Windows/Linux/macOS supported by Vivado)
• Nexys A7-100T board (device xc7a100tcsg324-1)
• USB cable and Digilent drivers (for programming via Vivado Hardware Manager)

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Quick Start (TL;DR)

1. Generate your ROM with the Assembler HTML (click Assemble → Download .zip).
2. Unzip the bundle somewhere (e.g., sap1_project/).
3. Add constraints: put your Nexys-A7-100T-Master.xdc into constraints/
   (keep only the nets you actually use uncommented).
4. From the project root, build:

   vivado -mode batch -source scripts/build_sap1_nexys_a7.tcl

5. Open Vivado (GUI), Hardware Manager → connect → Program Device with the generated .bit in:

   sap1_nexys_a7/sap1_nexys_a7.runs/impl_1/sap1_top.bit
   

6. Modify only the ROM and want a quick update? Run:

   vivado -mode batch -source scripts/rebuild_after_mem_change.tcl

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Detailed Steps

1) Create the project ZIP from the Assembler

• Open the provided SAP-1 Assembler web page.
• Write or paste your program (supports: LDA/ADDI/ADDM/SUBM/STA/OUTA/OUTI/HLT, plus .db).
• Click Assemble. Fix any errors shown.
• Click Download .zip to get a ready-to-build project.

2) Unzip the project

Unzip to a convenient folder, e.g.:

C:\\Projects\\sap1_project\\   (Windows)
~/projects/sap1_project/    (macOS/Linux)

3) Provide the board constraints

Place the official Digilent master XDC for the Nexys A7-100T into:

constraints/Nexys-A7-100T-Master.xdc

Then uncomment only the pins you use (LEDs, switches, buttons, seven-seg, VGA).

A minimal, clock-only XDC (sap1_minimal.xdc) is included and always added by the build script so you at least get a valid clock on pin E3 with a 100 MHz timing constraint.

4) Build from the command line

From the project root:

vivado -mode batch -source scripts/build_sap1_nexys_a7.tcl

What the script does:

• Creates a fresh project sap1_nexys_a7/ targeting xc7a100tcsg324-1
• Adds src/*.sv (SystemVerilog), the ROM file mem/sap1_rom.mem
• Adds constraints/sap1_minimal.xdc and (if present) your master XDC
• Runs synth → impl → write_bitstream

If successful, the bitstream is here:

sap1_nexys_a7/sap1_nexys_a7.runs/impl_1/sap1_top.bit

5) Program the board

• Open Vivado (GUI) → Open Hardware Manager
• Open target → Auto Connect
• Program device… → browse to sap1_top.bit and program

6) Fast rebuild when only ROM changes

If you only changed mem/sap1_rom.mem, you can skip project recreation:

vivado -mode batch -source scripts/rebuild_after_mem_change.tcl

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Top-Level & I/O

Top entity: sap1_top
Ports:

• CLK100MHZ (board oscillator, 100 MHz)
• RESETN (external reset, active-low)
• BTNC (reset button, active-high)
• BTNU (single-step button)
• BTND (run/pause toggle button)
• SW[15:0] (switches; reserved for future features)
• LED[15:0] (status; [7:0] mirrors internal “bus”, [8] run_mode, [9] halted)
• SEG[7:0] (CA..CG, DP; active-low)
• AN[7:0] (anodes; active-low; only AN0/AN1 used)
• VGA_HS, VGA_VS (syncs; active-low)
• VGA_R[3:0], VGA_G[3:0], VGA_B[3:0] (color outputs)

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VGA Output

This bundle includes a 640×480@~60Hz timing generator and a simple overlay that renders the OUT register as two large hex digits in cyan. If you prefer an exact 25.175 MHz pixel clock, swap the CE divider for a clk_wiz and adjust timing; most monitors tolerate the 25.000 MHz CE used here.

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Troubleshooting

• mem/sap1_rom.mem not found → Ensure it exists in mem/ (re-export from assembler if needed).
• Pins unconstrained → Include the master XDC and uncomment only used nets (LEDs, seven-seg, VGA).
• Wrong device → Scripts target xc7a100tcsg324-1; change to xc7a50tcsg324-1 if you use the A7-50T.

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Happy hacking! 🚀