Follow-up to #279.

Signed-off-by: Steven Bellock <sbellock@nvidia.com>

…ec-update

Spec update with synthesis warnings and jtag tck requirement

Update doe branch

updated property suite in hmac_drbg folder

Added formal folder with readme and pdf

Sha512 masked

initial markdown conversion of hardware spec

Merge dev-integrate -> main

Reintegrate main -> dev-msft

[FV] Adding ECC, DOE, HMAC_DRBG and SHA512_masked formal Assertion IP

initial hwspec images

APB defines are not meant to be user-configurable.

Signed-off-by: Steven Bellock <sbellock@nvidia.com>

Hardware Specification Headings

Update doc versions and release notes for 1.0-rc2 version

Extend new APB defines in integration document

Removed references to TSMC 5nm process. Closes #348 
Clarified reset rules section to reference cold boot flow to be easier to find for integrators. Closes #334 
Removed TODO from lint rules section. Closes #338

Clarifying backend convergence statement in integration requirements

Adding bootfsm brkpoint information

Removing hyphens for consistency

Update CaliptraIntegrationSpecification.md

Reintegrate main -> dev-msft

* Typo fix

* Resolve several TODO's by adding correct links

* Remove mailbox regs; clarify table of interrupt vectors

* Point to internal-regs in HW spec since describing Caliptra internal functionality

* Regenerate image from source to fix text

* Remove Fig. 18 TODO after updating img file

* Update heading link to eTRNG API section and remove TODO

* Fix syntax error on internal heading link

* Grammar: present tense

* Remove loaded 'official' term

* Caliptra RTL -> 'the RTL', better link to caliptra_defines.h

* More concise, informative verbiage on link to mbox_csr

* Full link name to mbox_csr for clarity

* remove profile for 1.0

* update figure numbers and minor text change

* Specify TRNG timing requirement

* Address #136

* Applied editorial feedback

Closes #262

* Updated SOC Integration Requirements - #291

* Updated SOC Integration Requirements - #291

* Addressed Editorial feedback for PR#357

* Addressed Editorial feedback for PR#357

* Replaced "Deobfuscation key" references with "Obfuscation key"

* Ensure that RISCV toolchain is installed

Internal-tag: [#53530]
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

* Use recommended RISC-V Toolchain in CI

Internal-tag: [#53530]
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

* Determine RISC-V toolchain version in GDB tests

Internal-tag: [#53530]
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

* Use more generic RISC-V toolchain references in README

Internal-tag: [#53530]
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

---------

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

* Add table to describe integrator/vendor module overrides

* relative path fix

* Add soc_ifc_pkg as file to modify

* Clarification on procedure for overriding native clock gate module

* Punctuation

* Change a word

* Formatting

* Clarified description of file modifications to be done by integrators

* hyphenate process-specific

* Add macro for RV core custom clock gating module

* Grammar updates from review

* Commas

The toolchain is hosted in the https://github.com/chipsalliance/caliptra-tools
repository

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

* updated ECC keygen TVLA documentation

* resolved the comments

* updated tvla png name

* Typo fix, release date same as file update date

Reintegrate main -> dev-msft

…24 hours

Increase ROM nightly regression timeout from 12 to 24 hours

Related work items: #602523

…ets reg is modified

Delay to let KV writes finish on all clients before clear_secrets reg is programmed to avoid reg update issues in UVM

Related work items: #602886

updating wait state count to 67 to accommodate perf bug in soc ifc arb

Wait state count worst case can last for two entire block reads from mailbox during the first/second block reads that occur with 2 clock delay (32 + 2 + 32 + 1)

two full block reads, 2 clock delay between, and 1 clock delay for SRAM read.

Related work items: #603171

…expected' txn

Resolve UVM prediction bug by calculating if txn is expected closer to performing the reset prediction. This catches a missing 'expected' signal transition on mailbox_data_avail during a reset edge case.

Related work items: #604229

…nternal

Manual file-copy sync from GH 'dev-msft' to MSFT internal repo.
Capture 1.0-rc2 updates for internal regressions.

Related work items: #604278

Add updates to improve code coverage in UVM regressions:
- Add extended checking in UVM regressions that throw errors for unexpected error interrupts from the SOC_IFC block (previously, the interrupts were serviced without being checked for context).
- Add randomization constraints to make interesting test values on PAUSER more likely to occur
- Update coverpoints for the RISC-V (VeeR) ECC error signals

Related work items: #608192

Demote UVM_ERROR to UVM_INFO on unexpected transactions between cptra_rst_b->cptra_noncore_rst_b (this is a legal scenario)

Related work items: #608843

Updates to UVM to delay KV clear by 1 clk when clear_secrets reg is set
Updates to sequence to turn on scan mode, perform writes and then turn off scan mode

Related work items: #609997

…fw upd rst

Add assertions for bus-idle condition during fw upd rst

Related work items: #610696

Reenable cg tests in L0 regression

Related work items: #610712

Disable verbose trace logs by default to reduce disk requirement for regressions
Also fix a typo in an assertion error message

Related work items: #611074, #613438

Dev msft 20240118