Avoid procedural wire assignment in test resource #979
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Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
aswaterman
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Jan 9, 2019
jackkoenig
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Feb 28, 2023
* Remove GhpagesPlugin. (#979) * Restore old SCM reference (after removing ghpages) * Remove reference to sbt-ghpages plugin.
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Running the tests with Verilator 4.008 (which Ubuntu apparently updated for me) will fail with a
PROCASSWIREerror due to an old Verilog test resource using this. Apparently the Verilog standard disallows procedural wire assignments and Verilator decided to hard align with this. This has odd implications as it effectively means that thealways @ *construct is effectively disabled. It's weird, but whatever.See: https://www.veripool.org/news/246-Verilator-Verilator-4-008-Released
Related issue:
Type of change: bug report
Impact: no functional change
Development Phase: implementation
Release Notes
This is a test-only fix, so no release notes.