![github-actions[bot]](https://avatars.githubusercontent.com/in/15368?v=4&size=40){kind=avatar}
1 file changed
+1
-1
lines changedSubmodule circt-verilog updated 13 files
- .github/bin/uploadReleaseArtifacts.sh+3
- .github/workflows/unifiedBuildTestAndInstall.yml+1-1
- .github/workflows/unifiedBuildTestAndInstallStatic.yml+1-1
- CMakeLists.txt-4
- cmake/modules/SlangCompilerOptions.cmake+5
- lib/Conversion/ExportVerilog/ExportVerilog.cpp+4-1
- lib/Dialect/ESI/runtime/python/esiaccel/cosim/simulator.py+159-35
- lib/Dialect/ESI/runtime/python/esiaccel/cosim/verilator.py+19-4
- lib/Tools/circt-verilog-lsp-server/VerilogServerImpl/VerilogServer.cpp+28
- test/Conversion/ExportVerilog/hw-dialect.mlir+8-8
- test/Conversion/ExportVerilog/verilog-basic.mlir+1-1
- test/Tools/circt-verilog-lsp-server/find-package-import-def.test+66
- test/circt-verilog/library-locations.sv+1-1
0 commit comments