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Fix BlackParrot synthesis in Synlig #5070

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robertszczepanski
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This PR applies a filelist patch for BlackParrot core in order to make it synthesizable in Synlig, the patch is the same as the one used in synlig. Even though test passes, logs show a lot of undriven wires and removed modules and this might require a closer look so I'm opening this as a draft PR for now to see if it behaves the same way in CI.

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Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
moore 0 0 0 0 4600
Slang_parse 0 0 0 0 4600
sv_parser 0 0 0 0 4600
VeribleExtractor 0 0 0 0 4509
Yosys 0 0 0 0 4663
moore_parse 0 0 0 0 4509
tree_sitter_verilog 0 0 0 0 4509
Verilator 0 0 0 0 4678
Icarus 0 0 0 0 4678
Sv2v_zachjs 0 0 0 0 4663
Slang 0 0 0 0 4663
Odin 0 0 0 0 4600
Surelog 0 0 0 0 4663
SynligYosys 0 0 0 0 4663
UhdmVerilator 0 0 0 0 4678
Verible 0 0 0 0 4509

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