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Added an always_wrap_module_instantiations flag #1909

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@jbylicki jbylicki commented May 5, 2023

This PR implements a new flag for the formatter: always_wrap_module_instantiations.
It forces module instantiations to be always split to new lines, instead of fitting it on line wherever possible. The default is set to false, which does not change the behavior of the formatter.

Fixes #1889
In there, the issue author suggested a two-state solution that I chose to implement.

Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
@jbylicki jbylicki force-pushed the add-module-instantiation-wrapping-options branch from f25c9f4 to a5216a1 Compare May 5, 2023 09:22
@jbylicki jbylicki requested a review from hzeller May 5, 2023 09:42
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codecov-commenter commented May 5, 2023

Codecov Report

Patch coverage: 100.00% and project coverage change: -0.31 ⚠️

Comparison is base (de4211b) 93.13% compared to head (8f33d2d) 92.82%.

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Additional details and impacted files
@@            Coverage Diff             @@
##           master    #1909      +/-   ##
==========================================
- Coverage   93.13%   92.82%   -0.31%     
==========================================
  Files         355      355              
  Lines       25843    26132     +289     
==========================================
+ Hits        24069    24258     +189     
- Misses       1774     1874     +100     
Impacted Files Coverage Δ
verilog/formatting/format_style.h 100.00% <ø> (ø)
verilog/formatting/format_style_init.cc 100.00% <100.00%> (ø)
verilog/formatting/tree_unwrapper.cc 95.08% <100.00%> (+0.40%) ⬆️

... and 16 files with indirect coverage changes

☔ View full report in Codecov by Sentry.
📢 Do you have feedback about the report comment? Let us know in this issue.

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hzeller commented May 17, 2023

Nice, can you update the Usage section in the README ?

(I think at some point we should have a documentation section with examples in the README that demonstrates the result of all flags. For some later PR :) ).

Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
verilog/formatting/formatter_test.cc Outdated Show resolved Hide resolved
verilog/formatting/tree_unwrapper.cc Outdated Show resolved Hide resolved
Co-authored-by: Mariusz Glebocki <mglb@arccos-1.net>
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
@jbylicki jbylicki force-pushed the add-module-instantiation-wrapping-options branch from e0115e0 to ea4656f Compare June 27, 2023 10:25
@jbylicki jbylicki requested a review from mglb June 27, 2023 10:53
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
@jbylicki jbylicki force-pushed the add-module-instantiation-wrapping-options branch from ea4656f to 8f33d2d Compare July 3, 2023 11:26
@mglb mglb self-requested a review July 4, 2023 13:09
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Instantiations Wrapped with One Port
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