Register duplication

[leonschoorl]

-- one register
f
    :: Clock System
    -> Reset System
    -> Signal System (Unsigned 8)
f clk rst = x
  where
    x :: Signal System (Unsigned 8)
    x = withClockResetEnable clk rst enableGen register 4 (x+1)


-- two registers
g
    :: Clock System
    -> Reset System
    -> Signal System (Unsigned 8)
g clk rst = withClockResetEnable clk rst enableGen x
  where
    x :: SystemClockResetEnable => Signal System (Unsigned 8)
    x = register 4 (x+1)

f work normally.
But the register in g duplicated in the HDL.