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trueDualPortBlockRam's logic is domain order agnostic implying possible cleanup #2352

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martijnbastiaan opened this issue Nov 7, 2022 · 0 comments
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trueDualPortBlockRam's logic is domain order agnostic implying possible cleanup #2352

martijnbastiaan opened this issue Nov 7, 2022 · 0 comments
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@martijnbastiaan
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After 212eb9a the model is domain order agnostic (?). AFAIK, we can therefore remove

clash-compiler/clash-prelude/src/Clash/Explicit/BlockRam.hs

Lines 1277 to 1281 in 3c3e185

trueDualPortBlockRam# clkA enA weA addrA datA clkB enB weB addrB datB
| snatToNum @Int (clockPeriod @domA) < snatToNum @Int (clockPeriod @domB)
= swap (trueDualPortBlockRamModel labelB clkB enB weB addrB datB labelA clkA enA weA addrA datA)
| otherwise
= trueDualPortBlockRamModel labelA clkA enA weA addrA datA labelB clkB enB weB addrB datB

@martijnbastiaan martijnbastiaan mentioned this issue Nov 7, 2022
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martijnbastiaan added a commit that referenced this issue Mar 2, 2023
@martijnbastiaan
Remove domain ordering from 'trueDualPortBlockRam'
ab8010a 
Previous commits have removed the clock domain ordering sensitivity from
the TDP BRAM model, but didn't remove the wrapper, nor the hack
prepending `ClockB` to the result of `clockTicks`.

Closes #2352
martijnbastiaan added a commit that referenced this issue Mar 15, 2023
@martijnbastiaan
Remove domain ordering from 'trueDualPortBlockRam'
2b36bd5 
Previous commits have removed the clock domain ordering sensitivity from
the TDP BRAM model, but didn't remove the wrapper, nor the hack
prepending `ClockB` to the result of `clockTicks`.

Closes #2352
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