Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

DSL.instDecl is very Verilog-focused when it comes to generic/parameter passing #2471

Closed
martijnbastiaan opened this issue May 17, 2023 · 1 comment
Closed

DSL.instDecl is very Verilog-focused when it comes to generic/parameter passing #2471

martijnbastiaan opened this issue May 17, 2023 · 1 comment
Assignees
@martijnbastiaan
Labels
enhancement

Comments

@martijnbastiaan
Copy link
Member

In particular:

clash-compiler/clash-lib/src/Clash/Primitives/DSL.hs

Lines 790 to 791 in 70d2b1f

-> [(Text, LitHDL)]
-- ^ attributes

VHDL allows more types than LitHDL can represent. (Also: "attributes" is a misnomer here.)
@martijnbastiaan martijnbastiaan self-assigned this May 17, 2023
@martijnbastiaan martijnbastiaan mentioned this issue May 17, 2023
Closed
martijnbastiaan added a commit that referenced this issue May 23, 2023
@martijnbastiaan
Accept TExpr in instDecl's paramater argument
8f97548 
Fixes #2471
@christiaanb
Copy link
Member

We've released v1.8.0, which includes a fix for this issue.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@martijnbastiaan martijnbastiaan

Labels
enhancement
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@christiaanb @martijnbastiaan