VHDL: no div/rem/mod by zero in gen'd code #1873
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christiaanb
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Nice work on all the fixes, could you add changelogs? :) |
Because Clash translates to concurrent assignments, things like ``` if y /= 0 then quot x y else 0 ``` would result in a VHDL sim error (at least on GHDL) because all subterms of the if-then-else expression would be evaluated concurrently, and `x / y` would throw a sim error whenever `y=0` even though that result could never be observed. So now, for the division operators we add the following: ``` -- pragma translate_off when (y /= 0) else (others => 'X') -- pragma translate_on ``` To ensure the division by zero exception isn't thrown during VHDL simulation.
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martijnbastiaan
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Jul 14, 2021
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Because Clash translates to concurrent assignments, things like
would result in a VHDL sim error (at least on GHDL) because all subterms of the if-then-else expression would be evaluated
concurrently, and
x / ywould throw a sim error whenevery=0even though that result could never be observed.