Netlist track usage #2230

alex-mckenna · 2022-05-31T14:26:22Z

When producing sequential and concurrent code, there are restrictions for how the same declared signal can be assigned which depend on the HDL being targeted. In short, these are

VHDL: A signal can be assigned continuously, or procedurally with non-blocking assignment. A variable can only be assigned procedurally with blocking assignment.
Verilog: A wire can only be assigned continuously. A reg can only be assigned procedurally, but can be assigned both non-blocking and blocking.

When the backend produces HDL, it needs to know the type of a declaration to render it. With the WireOrReg type, this was easy for VHDL, but does not help differentiate between if a signal is intended to be a VHDL signal or variable. A more general type is now provided which provides the extra information to make this choice:

data Blocking = Blocking | NonBlocking
data Usage    = Cont | Proc Blocking

Since a declaration can accept more than one type of assignment, the usage is not tracked with the declaration like WireOrReg was, but tracked in the assignments and a usage map is created for every component (tracking declared signals to their most restrictive use). When producing netlist, the current use of a signal should be checked to ensure that generated code only produces assignments that are valid for the backend being targeted.

Still TODO:

Write a changelog entry (see changelog/README.md)
Check copyright notices are up to date in edited files

clash-lib/src/Clash/Netlist/BlackBox/Util.hs

clash-lib/src/Clash/Netlist/Types.hs

clash-lib/src/Clash/Netlist/Types.hs-boot

clash-lib/src/Clash/Netlist/Util.hs

clash-lib/src/Clash/Primitives/Types.hs

leonschoorl

See ^

martijnbastiaan

LGTM, but it'd be great if @christiaanb could give this a glance too.

clash-lib/src/Clash/Netlist/Types.hs

In NetDecl', the type of the decl was either a HWType or raw text. Since only the HWType branch was ever used in Clash, this should be simplified.

The function `id2identifier` is an unsafe version of `fromCoreId` in the netlist identifier module. It makes more sense for it to be defined there, so callers can see it is obviously unsafe.

When producing sequential and concurrent code, there are restrictions for how the same declared signal can be assigned which depend on the HDL being targeted. In short, these are VHDL: A `signal` can be assigned continuously, or procedurally with non-blocking assignment. A `variable` can only be assigned procedurally with blocking assignment. Verilog: A `wire` can only be assigned continuously. A `reg` can only be assigned procedurally, but can be assigned both non-blocking and blocking. When the backend produces HDL, it needs to know the type of a declaration to render it. With the `WireOrReg` type, this was easy for VHDL, but does not help differentiate between if a signal is intended to be a VHDL signal or variable. A more general type is now provided which provides the extra information to make this choice: ```haskell data Blocking = Blocking | NonBlocking data Usage = Cont | Proc Blocking ``` Since a declaration can accept more than one type of assignment, the usage is not tracked with the declaration like `WireOrReg` was, but tracked in the assignments and a usage map is created for every component (tracking declared signals to their most restrictive use). When producing netlist, the current use of a signal should be checked to ensure that generated code only produces assignments that are valid for the backend being targeted.

alex-mckenna added the needs-review label May 31, 2022

alex-mckenna force-pushed the netlist-track-usage branch 4 times, most recently from cb665f9 to 5f90376 Compare June 1, 2022 09:09

alex-mckenna mentioned this pull request Jun 1, 2022

(Optionally) Sequential Black Boxes #2231

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