[rocky9_6] History Rebuild for kernel-5.14.0-570.18.1.el9_6

Makefile.rhelver

@@ -12,7 +12,7 @@ RHEL_MINOR = 6
 #
 # Use this spot to avoid future merge conflicts.
 # Do not trim this comment.
-RHEL_RELEASE = 570.17.1
+RHEL_RELEASE = 570.18.1
 
 #
 # ZSTREAM

ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/802a69b6.failed

@@ -0,0 +1,40 @@
+drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation
+
+jira NONE_AUTOMATION
+Rebuild_History Non-Buildable kernel-5.14.0-570.18.1.el9_6
+commit-author Imre Deak <imre.deak@intel.com>
+commit 802a69b6b8a0502a9e2309afec7e1b77f67874f2
+Empty-Commit: Cherry-Pick Conflicts during history rebuild.
+Will be included in final tarball splat. Ref for failed cherry-pick at:
+ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/802a69b6.failed
+
+The MST branch device may not support the number of DSC slices a mode
+requires, handle the error in this case.
+
+Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation")
+	Cc: stable@vger.kernel.org # v6.8+
+	Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+	Signed-off-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-1-imre.deak@intel.com
+(cherry picked from commit 802a69b6b8a0502a9e2309afec7e1b77f67874f2)
+	Signed-off-by: Jonathan Maple <jmaple@ciq.com>
+
+# Conflicts:
+#	drivers/gpu/drm/i915/display/intel_dp_mst.c
+diff --cc drivers/gpu/drm/i915/display/intel_dp_mst.c
+index 3dc3c85fef64,2822ae116003..000000000000
+--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
+@@@ -152,7 -153,7 +152,11 @@@ static int intel_dp_mst_dsc_get_slice_c
+  {
+  	const struct drm_display_mode *adjusted_mode =
+  		&crtc_state->hw.adjusted_mode;
+++<<<<<<< HEAD
+ +	int num_joined_pipes = crtc_state->joiner_pipes;
+++=======
++ 	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
+++>>>>>>> 802a69b6b8a0 (drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation)
+
+  	return intel_dp_dsc_get_slice_count(connector,
+  					    adjusted_mode->clock,
+* Unmerged path drivers/gpu/drm/i915/display/intel_dp_mst.c

ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/f2e2092a.failed

@@ -0,0 +1,190 @@
+drm/i915/display: Use joined pipes in dsc helpers for slices, bpp
+
+jira NONE_AUTOMATION
+Rebuild_History Non-Buildable kernel-5.14.0-570.18.1.el9_6
+commit-author Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+commit f2e2092a979cd46b43445daf23628015ac776ac3
+Empty-Commit: Cherry-Pick Conflicts during history rebuild.
+Will be included in final tarball splat. Ref for failed cherry-pick at:
+ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/f2e2092a.failed
+
+In preparation of ultrajoiner, use number of joined pipes in the dsc
+helpers to compute dsc slices and max compressed bpp, instead of using
+the joiner flag.
+
+v2: Adjust the formulae to use num of pipes as 1 (no joiner) or 2
+(bigjoiner). (Ankit)
+
+	Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+	Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> (v1)
+	Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240916102836.2149012-5-ankit.k.nautiyal@intel.com
+(cherry picked from commit f2e2092a979cd46b43445daf23628015ac776ac3)
+	Signed-off-by: Jonathan Maple <jmaple@ciq.com>
+
+# Conflicts:
+#	drivers/gpu/drm/i915/display/intel_dp_mst.c
+diff --cc drivers/gpu/drm/i915/display/intel_dp_mst.c
+index 3dc3c85fef64,dc050da29815..000000000000
+--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
+@@@ -100,8 -101,15 +100,20 @@@ static int intel_dp_mst_bw_overhead(con
+  	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
+  	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
+
+++<<<<<<< HEAD
+ +	if (dsc_slice_count)
+ +		flags |= DRM_DP_BW_OVERHEAD_DSC;
+++=======
++ 	if (dsc) {
++ 		int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
++ 
++ 		flags |= DRM_DP_BW_OVERHEAD_DSC;
++ 		dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
++ 							       adjusted_mode->clock,
++ 							       adjusted_mode->hdisplay,
++ 							       num_joined_pipes);
++ 	}
+++>>>>>>> f2e2092a979c (drm/i915/display: Use joined pipes in dsc helpers for slices, bpp)
+
+  	overhead = drm_dp_bw_overhead(crtc_state->lane_count,
+  				      adjusted_mode->hdisplay,
+diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
+index 5e17097f703b..e50ed7526f2c 100644
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -868,14 +868,14 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
+ static
+ u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ 				       u32 mode_clock, u32 mode_hdisplay,
+-				       bool bigjoiner)
++				       int num_joined_pipes)
+ {
+ 	u32 max_bpp_small_joiner_ram;
+
+ 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
+
+-	if (bigjoiner) {
++	if (num_joined_pipes == 2) {
+ 		int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ 		/* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
+ 		int ppc = 2;
+@@ -894,7 +894,7 @@ u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ 					u32 link_clock, u32 lane_count,
+ 					u32 mode_clock, u32 mode_hdisplay,
+-					bool bigjoiner,
++					int num_joined_pipes,
+ 					enum intel_output_format output_format,
+ 					u32 pipe_bpp,
+ 					u32 timeslots)
+@@ -940,7 +940,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ 				intel_dp_mode_to_fec_clock(mode_clock));
+
+ 	joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+-							    mode_hdisplay, bigjoiner);
++							    mode_hdisplay, num_joined_pipes);
+ 	bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
+
+ 	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
+@@ -950,7 +950,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+
+ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
+ 				int mode_clock, int mode_hdisplay,
+-				bool bigjoiner)
++				int num_joined_pipes)
+ {
+ 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ 	u8 min_slice_count, i;
+@@ -984,14 +984,14 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
+
+ 	/* Find the closest match to the valid slice count values */
+ 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
+-		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
++		u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
+
+ 		if (test_slice_count >
+ 		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
+ 			break;
+
+ 		/* big joiner needs small joiner to be enabled */
+-		if (bigjoiner && test_slice_count < 4)
++		if (num_joined_pipes == 2 && test_slice_count < 4)
+ 			continue;
+
+ 		if (min_slice_count <= test_slice_count)
+@@ -1390,14 +1390,14 @@ intel_dp_mode_valid(struct drm_connector *_connector,
+ 								    max_lanes,
+ 								    target_clock,
+ 								    mode->hdisplay,
+-								    joiner,
++								    num_joined_pipes,
+ 								    output_format,
+ 								    pipe_bpp, 64);
+ 			dsc_slice_count =
+ 				intel_dp_dsc_get_slice_count(connector,
+ 							     target_clock,
+ 							     mode->hdisplay,
+-							     joiner);
++							     num_joined_pipes);
+ 		}
+
+ 		dsc = dsc_max_compressed_bpp && dsc_slice_count;
+@@ -2113,6 +2113,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ 	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ 	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ 	int dsc_joiner_max_bpp;
++	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
+
+ 	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ 	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
+@@ -2127,7 +2128,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+
+ 	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
+ 								adjusted_mode->hdisplay,
+-								pipe_config->joiner_pipes);
++								num_joined_pipes);
+ 	dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+ 	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
+
+@@ -2312,6 +2313,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
+ 		to_intel_connector(conn_state->connector);
+ 	const struct drm_display_mode *adjusted_mode =
+ 		&pipe_config->hw.adjusted_mode;
++	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
+ 	int ret;
+
+ 	pipe_config->fec_enable = pipe_config->fec_enable ||
+@@ -2361,7 +2363,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
+ 			intel_dp_dsc_get_slice_count(connector,
+ 						     adjusted_mode->crtc_clock,
+ 						     adjusted_mode->crtc_hdisplay,
+-						     pipe_config->joiner_pipes);
++						     num_joined_pipes);
+ 		if (!dsc_dp_slice_count) {
+ 			drm_dbg_kms(&dev_priv->drm,
+ 				    "Compressed Slice Count not supported\n");
+diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
+index 3aef57dd463a..a0a31fb64716 100644
+--- a/drivers/gpu/drm/i915/display/intel_dp.h
++++ b/drivers/gpu/drm/i915/display/intel_dp.h
+@@ -143,7 +143,7 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
+ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ 					u32 link_clock, u32 lane_count,
+ 					u32 mode_clock, u32 mode_hdisplay,
+-					bool bigjoiner,
++					int num_joined_pipes,
+ 					enum intel_output_format output_format,
+ 					u32 pipe_bpp,
+ 					u32 timeslots);
+@@ -153,7 +153,7 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector
+ 					 int bpc);
+ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
+ 				int mode_clock, int mode_hdisplay,
+-				bool bigjoiner);
++				int num_joined_pipes);
+ bool intel_dp_need_joiner(struct intel_dp *intel_dp,
+ 			  struct intel_connector *connector,
+ 			  int hdisplay, int clock);
+* Unmerged path drivers/gpu/drm/i915/display/intel_dp_mst.c

ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/rebuild.details.txt

@@ -0,0 +1,21 @@
+Rebuild_History BUILDABLE
+Rebuilding Kernel from rpm changelog with Fuzz Limit: 87.50%
+Number of commits in upstream range v5.14~1..kernel-mainline: 306894
+Number of commits in rpm: 14
+Number of commits matched with upstream: 11 (78.57%)
+Number of commits in upstream but not in rpm: 306885
+Number of commits NOT found in upstream: 3 (21.43%)
+
+Rebuilding Kernel on Branch rocky9_6_rebuild_kernel-5.14.0-570.18.1.el9_6 for kernel-5.14.0-570.18.1.el9_6
+Clean Cherry Picks: 7 (63.64%)
+Empty Cherry Picks: 2 (18.18%)
+_______________________________
+
+__EMPTY COMMITS__________________________
+f2e2092a979cd46b43445daf23628015ac776ac3 drm/i915/display: Use joined pipes in dsc helpers for slices, bpp
+802a69b6b8a0502a9e2309afec7e1b77f67874f2 drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation
+
+__CHANGES NOT IN UPSTREAM________________
+Porting to Rocky Linux 9, debranding and Rocky branding'
+Ensure aarch64 kernel is not compressed'
+gitlab-ci: use rhel9.6 builder image