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4 followers · 9 following · 23

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@vim-china

Popular repositories

  1. asyn_fifo

    异步fifo模块

    Verilog 2 2

  2. catch_QB

    Python 1

  3. openmsp430

    Forked from freecores/openmsp430

    openMSP430

    Verilog

  4. sublime

    我的sublime编辑器

    Python

  5. sublime-user

    我的安装版sublime

    JavaScript

  6. mod_sim

    Verilog

17 contributions in the last year

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Contribution activity

April 2021

cxhy has no activity yet for this period.

March 2021

Created 1 commit in 1 repository

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