[CR][Intel] Changed specs to L1 NPP Prefetcher

README.md

@@ -520,7 +520,7 @@ parm:           Custom_TDC_Offset:TDC Limit Offset (amp) (short)
 parm:           Activate_TDC_Limit:Activate TDC Limiting (short)
 parm:           L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short)
 parm:           L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short)
-parm:           L1_NLP_PREFETCH_Disable:Disable L1 NLP Prefetcher (short)
+parm:           L1_NPP_PREFETCH_Disable:Disable L1 NPP Prefetcher (short)
 parm:           L1_Scrubbing_Enable:Enable L1 Scrubbing (short)
 parm:           L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short)
 parm:           L2_HW_CL_PREFETCH_Disable:Disable L2 HW CL Prefetcher (short)

x86_64/corefreq-api.h

@@ -1037,7 +1037,7 @@ typedef struct
 	BitCC			ODCM		__attribute__ ((aligned (16)));
 	BitCC			L1_HW_Prefetch	__attribute__ ((aligned (16)));
 	BitCC			L1_HW_IP_Prefetch __attribute__((aligned (16)));
-	BitCC	/* Intel */	L1_NLP_Prefetch __attribute__ ((aligned (16)));
+	BitCC	/* Intel */	L1_NPP_Prefetch __attribute__ ((aligned (16)));
 	BitCC	/* Intel */	L1_Scrubbing	__attribute__ ((aligned (16)));
 	BitCC			L2_HW_Prefetch	__attribute__ ((aligned (16)));
 	BitCC			L2_HW_CL_Prefetch __attribute__((aligned (16)));

x86_64/corefreq-cli-json.c

@@ -1507,8 +1507,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_HW_Prefetch);
 			json_key(&s, "L1_HW_IP_Prefetch");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch);
-			json_key(&s, "L1_NLP_Prefetch");
-			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_NLP_Prefetch);
+			json_key(&s, "L1_NPP_Prefetch");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_NPP_Prefetch);
 			json_key(&s, "L1_Scrubbing");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_Scrubbing);
 			json_key(&s, "L2_HW_Prefetch");

x86_64/corefreq-cli-rsc-en.h

@@ -1214,7 +1214,7 @@
 #define RSC_TECHNOLOGIES_PF_CODE_EN	"Cache Prefetchers"
 #define RSC_TECH_L1_HW_PREFETCH_CODE_EN "L1 Prefetcher"
 #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_EN "L1 IP Prefetcher"
-#define RSC_TECH_L1_NLP_PREFETCH_CODE_EN "L1 Next Line Prefetcher"
+#define RSC_TECH_L1_NPP_PREFETCH_CODE_EN "L1 Next Page Prefetcher"
 #define RSC_TECH_L1_SCRUBBING_CODE_EN	"L1 Scrubbing"
 #define RSC_TECH_L2_HW_PREFETCH_CODE_EN "L2 Prefetcher"
 #define RSC_TECH_L2_HW_CL_PREFETCH_CODE_EN "L2 Adjacent Cache Line Prefetcher"
@@ -2175,7 +2175,7 @@
 
 #define RSC_BOX_CU_L1_TITLE_CODE	" Cache Unit L1 Prefetcher "
 #define RSC_BOX_CU_L1_IP_TITLE_CODE	" Cache Unit L1 IP Prefetcher "
-#define RSC_BOX_CU_L1_NLP_TITLE_CODE	" Cache Unit L1 NLP Prefetcher "
+#define RSC_BOX_CU_L1_NPP_TITLE_CODE	" Cache Unit L1 NPP Prefetcher "
 #define RSC_BOX_L1_SCRUBBING_TITLE_CODE " Cache Unit L1 Scrubbing "
 #define RSC_BOX_CU_L2_TITLE_CODE	" Cache Unit L2 Prefetcher "
 #define RSC_BOX_CU_L2_CL_TITLE_CODE	" Cache Unit L2 CL Prefetcher "

x86_64/corefreq-cli-rsc-fr.h

@@ -688,7 +688,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_TECHNOLOGIES_PF_CODE_FR	"Pr""\xa9""lecteur de Caches"
 #define RSC_TECH_L1_HW_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1"
 #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 IP"
-#define RSC_TECH_L1_NLP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 ligne suivante"
+#define RSC_TECH_L1_NPP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 page suivante"
 #define RSC_TECH_L1_SCRUBBING_CODE_FR	"L1 Scrubbing"
 #define RSC_TECH_L2_HW_PREFETCH_CODE_FR  "Pr""\xa9""lecteur L2"
 #define RSC_TECH_L2_HW_CL_PREFETCH_CODE_FR "Pr""\xa9""lecteur L2 ligne de cache"

x86_64/corefreq-cli-rsc.c

@@ -1105,7 +1105,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_TECHNOLOGIES_PF),
 	LDT(RSC_TECH_L1_HW_PREFETCH),
 	LDT(RSC_TECH_L1_HW_IP_PREFETCH),
-	LDT(RSC_TECH_L1_NLP_PREFETCH),
+	LDT(RSC_TECH_L1_NPP_PREFETCH),
 	LDT(RSC_TECH_L1_SCRUBBING),
 	LDT(RSC_TECH_L2_HW_PREFETCH),
 	LDT(RSC_TECH_L2_HW_CL_PREFETCH),
@@ -1782,7 +1782,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_BOX_MODE_DESC),
 	LDQ(RSC_BOX_CU_L1_TITLE),
 	LDQ(RSC_BOX_CU_L1_IP_TITLE),
-	LDQ(RSC_BOX_CU_L1_NLP_TITLE),
+	LDQ(RSC_BOX_CU_L1_NPP_TITLE),
 	LDQ(RSC_BOX_L1_SCRUBBING_TITLE),
 	LDQ(RSC_BOX_CU_L2_TITLE),
 	LDQ(RSC_BOX_CU_L2_CL_TITLE),

x86_64/corefreq-cli-rsc.h

@@ -908,7 +908,7 @@ enum {
 	RSC_TECHNOLOGIES_PF,
 	RSC_TECH_L1_HW_PREFETCH,
 	RSC_TECH_L1_HW_IP_PREFETCH,
-	RSC_TECH_L1_NLP_PREFETCH,
+	RSC_TECH_L1_NPP_PREFETCH,
 	RSC_TECH_L1_SCRUBBING,
 	RSC_TECH_L2_HW_PREFETCH,
 	RSC_TECH_L2_HW_CL_PREFETCH,
@@ -1585,7 +1585,7 @@ enum {
 	RSC_BOX_MODE_DESC,
 	RSC_BOX_CU_L1_TITLE,
 	RSC_BOX_CU_L1_IP_TITLE,
-	RSC_BOX_CU_L1_NLP_TITLE,
+	RSC_BOX_CU_L1_NPP_TITLE,
 	RSC_BOX_L1_SCRUBBING_TITLE,
 	RSC_BOX_CU_L2_TITLE,
 	RSC_BOX_CU_L2_CL_TITLE,

x86_64/corefreq-cli.c

@@ -3778,9 +3778,9 @@ void L1_HW_IP_Prefetch_Update(TGrid *grid, DATA_TYPE data[])
 	TechUpdate(grid, bix, pos, 3, ENABLED(bix));
 }
 
-void L1_NLP_Prefetch_Update(TGrid *grid, DATA_TYPE data[])
+void L1_NPP_Prefetch_Update(TGrid *grid, DATA_TYPE data[])
 {
-	const unsigned int bix = RO(Shm)->Proc.Technology.L1_NLP_Prefetch == 1;
+	const unsigned int bix = RO(Shm)->Proc.Technology.L1_NPP_Prefetch == 1;
 	const signed int pos = grid->cell.length - 5;
 	UNUSED(data);
 
@@ -4025,13 +4025,13 @@ REASON_CODE SysInfoTech(Window *win,
 	},
 	{
 		(unsigned int[]) { CRC_INTEL, 0 },
-		RO(Shm)->Proc.Technology.L1_NLP_Prefetch,
-		3, "%s%.*sL1 NLP   <%3s>",
-		RSC(TECH_L1_NLP_PREFETCH).CODE(), NULL,
-		width - (OutFunc ? 18 : 20) - RSZ(TECH_L1_NLP_PREFETCH),
+		RO(Shm)->Proc.Technology.L1_NPP_Prefetch,
+		3, "%s%.*sL1 NPP   <%3s>",
+		RSC(TECH_L1_NPP_PREFETCH).CODE(), NULL,
+		width - (OutFunc ? 18 : 20) - RSZ(TECH_L1_NPP_PREFETCH),
 		NULL,
-		BOXKEY_L1_NLP_PREFETCH,
-		L1_NLP_Prefetch_Update
+		BOXKEY_L1_NPP_PREFETCH,
+		L1_NPP_Prefetch_Update
 	},
 	{
 		(unsigned int[]) { CRC_INTEL, 0 },
@@ -13732,7 +13732,7 @@ int Shortcut(SCANKEY *scan)
 	}
     break;
 
-    case BOXKEY_L1_NLP_PREFETCH:
+    case BOXKEY_L1_NPP_PREFETCH:
     {
 	Window *win = SearchWinListById(scan->key, &winList);
       if (win == NULL)
@@ -13742,18 +13742,18 @@ int Shortcut(SCANKEY *scan)
 		.row = TOP_HEADER_ROW + 3
 	}, select = {
 		.col = 0,
-		.row = RO(Shm)->Proc.Technology.L1_NLP_Prefetch ? 2 : 1
+		.row = RO(Shm)->Proc.Technology.L1_NPP_Prefetch ? 2 : 1
 	};
 	AppendWindow(
 		CreateBox(scan->key, origin, select,
-				(char*) RSC(BOX_CU_L1_NLP_TITLE).CODE(),
+				(char*) RSC(BOX_CU_L1_NPP_TITLE).CODE(),
 			RSC(BOX_BLANK_DESC).CODE(), blankAttr,	SCANKEY_NULL,
-			stateStr[1][RO(Shm)->Proc.Technology.L1_NLP_Prefetch],
-			stateAttr[RO(Shm)->Proc.Technology.L1_NLP_Prefetch],
-						BOXKEY_L1_NLP_PREFETCH_ON,
-		       stateStr[0][!RO(Shm)->Proc.Technology.L1_NLP_Prefetch],
-			stateAttr[!RO(Shm)->Proc.Technology.L1_NLP_Prefetch],
-						BOXKEY_L1_NLP_PREFETCH_OFF,
+			stateStr[1][RO(Shm)->Proc.Technology.L1_NPP_Prefetch],
+			stateAttr[RO(Shm)->Proc.Technology.L1_NPP_Prefetch],
+						BOXKEY_L1_NPP_PREFETCH_ON,
+		       stateStr[0][!RO(Shm)->Proc.Technology.L1_NPP_Prefetch],
+			stateAttr[!RO(Shm)->Proc.Technology.L1_NPP_Prefetch],
+						BOXKEY_L1_NPP_PREFETCH_OFF,
 			RSC(BOX_BLANK_DESC).CODE(), blankAttr,	SCANKEY_NULL),
 		&winList);
       } else {
@@ -13762,21 +13762,21 @@ int Shortcut(SCANKEY *scan)
     }
     break;
 
-    case BOXKEY_L1_NLP_PREFETCH_OFF:
+    case BOXKEY_L1_NPP_PREFETCH_OFF:
 	if (!RING_FULL(RW(Shm)->Ring[0])) {
 		RING_WRITE(	RW(Shm)->Ring[0],
 				COREFREQ_IOCTL_TECHNOLOGY,
 				COREFREQ_TOGGLE_OFF,
-				TECHNOLOGY_L1_NLP_PREFETCH );
+				TECHNOLOGY_L1_NPP_PREFETCH );
 	}
     break;
 
-    case BOXKEY_L1_NLP_PREFETCH_ON:
+    case BOXKEY_L1_NPP_PREFETCH_ON:
 	if (!RING_FULL(RW(Shm)->Ring[0])) {
 		RING_WRITE(	RW(Shm)->Ring[0],
 				COREFREQ_IOCTL_TECHNOLOGY,
 				COREFREQ_TOGGLE_ON,
-				TECHNOLOGY_L1_NLP_PREFETCH );
+				TECHNOLOGY_L1_NPP_PREFETCH );
 	}
     break;
 

x86_64/corefreq-cli.h

@@ -288,9 +288,9 @@ enum KEY_ENUM {
   BOXKEY_L1_BURST_PREFETCH	= 0x3000000000004800LLU,
   BOXKEY_L1_BURST_PF_OFF	= 0x3000000000004801LLU,
   BOXKEY_L1_BURST_PF_ON 	= 0x3000000000004802LLU,
-  BOXKEY_L1_NLP_PREFETCH	= 0x3000000000004810LLU,
-  BOXKEY_L1_NLP_PREFETCH_OFF	= 0x3000000000004811LLU,
-  BOXKEY_L1_NLP_PREFETCH_ON	= 0x3000000000004812LLU,
+  BOXKEY_L1_NPP_PREFETCH	= 0x3000000000004810LLU,
+  BOXKEY_L1_NPP_PREFETCH_OFF	= 0x3000000000004811LLU,
+  BOXKEY_L1_NPP_PREFETCH_ON	= 0x3000000000004812LLU,
   BOXKEY_L2_STREAM_HW_PREFETCH	= 0x3000000000004820LLU,
   BOXKEY_L2_STREAM_HW_PF_OFF	= 0x3000000000004821LLU,
   BOXKEY_L2_STREAM_HW_PF_ON	= 0x3000000000004822LLU,
@@ -691,9 +691,9 @@ int CheckDuplicateKey(void)			\
 	case BOXKEY_L1_BURST_PREFETCH:		\
 	case BOXKEY_L1_BURST_PF_OFF:		\
 	case BOXKEY_L1_BURST_PF_ON:		\
-	case BOXKEY_L1_NLP_PREFETCH:		\
-	case BOXKEY_L1_NLP_PREFETCH_OFF:	\
-	case BOXKEY_L1_NLP_PREFETCH_ON: 	\
+	case BOXKEY_L1_NPP_PREFETCH:		\
+	case BOXKEY_L1_NPP_PREFETCH_OFF:	\
+	case BOXKEY_L1_NPP_PREFETCH_ON: 	\
 	case BOXKEY_L2_STREAM_HW_PREFETCH:	\
 	case BOXKEY_L2_STREAM_HW_PF_OFF:	\
 	case BOXKEY_L2_STREAM_HW_PF_ON:		\

x86_64/corefreq.h

@@ -358,7 +358,7 @@ typedef struct
 				WDT		: 29-28,
 				TM1		: 31-29,
 				TM2		: 33-31,
-				L1_NLP_Prefetch : 34-33,
+				L1_NPP_Prefetch : 34-33,
 				L1_Scrubbing	: 35-34,
 				L2_AMP_Prefetch : 36-35,
 				L2_NLP_Prefetch : 37-36,

x86_64/corefreqd.c

@@ -1618,8 +1618,8 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
 						RW(Proc)->L1_HW_IP_Prefetch,
 						RO(Proc)->DCU_Mask);
 
-	RO(Shm)->Proc.Technology.L1_NLP_Prefetch = BITCMP_CC(LOCKLESS,
-						RW(Proc)->L1_NLP_Prefetch,
+	RO(Shm)->Proc.Technology.L1_NPP_Prefetch = BITCMP_CC(LOCKLESS,
+						RW(Proc)->L1_NPP_Prefetch,
 						RO(Proc)->DCU_Mask);
 
 	RO(Shm)->Proc.Technology.L1_Scrubbing = BITWISEAND_CC(LOCKLESS,

x86_64/corefreqk.c

@@ -199,9 +199,9 @@ static signed short L1_HW_IP_PREFETCH_Disable = -1;
 module_param(L1_HW_IP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(L1_HW_IP_PREFETCH_Disable, "Disable L1 HW IP Prefetcher");
 
-static signed short L1_NLP_PREFETCH_Disable = -1;
-module_param(L1_NLP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
-MODULE_PARM_DESC(L1_NLP_PREFETCH_Disable, "Disable L1 NLP Prefetcher");
+static signed short L1_NPP_PREFETCH_Disable = -1;
+module_param(L1_NPP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
+MODULE_PARM_DESC(L1_NPP_PREFETCH_Disable, "Disable L1 NPP Prefetcher");
 
 static signed short L1_Scrubbing_Enable = -1;
 module_param(L1_Scrubbing_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
@@ -9053,10 +9053,10 @@ void Intel_DCU_Technology(CORE_RO *Core)			/*Per Core */
 		ToggleFeature = 1;
 		break;
 	}
-	switch (L1_NLP_PREFETCH_Disable) {
+	switch (L1_NPP_PREFETCH_Disable) {
 	case COREFREQ_TOGGLE_OFF:
 	case COREFREQ_TOGGLE_ON:
-		MiscFeatCtrl.L1_NLP_Prefetch = L1_NLP_PREFETCH_Disable;
+		MiscFeatCtrl.L1_NPP_Prefetch = L1_NPP_PREFETCH_Disable;
 		ToggleFeature = 1;
 		break;
 	}
@@ -9085,10 +9085,10 @@ void Intel_DCU_Technology(CORE_RO *Core)			/*Per Core */
     } else {
 	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch, Core->Bind);
     }
-    if (MiscFeatCtrl.L1_NLP_Prefetch == 1) {
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NLP_Prefetch, Core->Bind);
+    if (MiscFeatCtrl.L1_NPP_Prefetch == 1) {
+	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
     } else {
-	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NLP_Prefetch, Core->Bind);
+	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
     }
 	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask, Core->Bind);
 
@@ -9128,7 +9128,6 @@ void Intel_DCU_Technology(CORE_RO *Core)			/*Per Core */
       } else {
 	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->LLC_Streamer, Core->Bind);
       }
-
 	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->ECORE_Mask, Core->Bind);
      }
 	break;
@@ -12316,7 +12315,7 @@ void PerCore_Reset(CORE_RO *Core)
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->ODCM	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_Prefetch	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch , Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NLP_Prefetch	, Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_Prefetch	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_CL_Prefetch , Core->Bind);
@@ -22047,14 +22046,14 @@ static long CoreFreqK_ioctl(	struct file *filp,
 		}
 		break;
 
-	case TECHNOLOGY_L1_NLP_PREFETCH:
+	case TECHNOLOGY_L1_NPP_PREFETCH:
 		switch (prm.dl.lo) {
 		case COREFREQ_TOGGLE_OFF:
 		case COREFREQ_TOGGLE_ON:
 			Controller_Stop(1);
-			L1_NLP_PREFETCH_Disable = !prm.dl.lo;
+			L1_NPP_PREFETCH_Disable = !prm.dl.lo;
 			Controller_Start(1);
-			L1_NLP_PREFETCH_Disable = -1;
+			L1_NPP_PREFETCH_Disable = -1;
 			rc = RC_SUCCESS;
 			break;
 		}

x86_64/coretypes.h

@@ -2550,7 +2550,7 @@ enum {
 	TECHNOLOGY_R2H,
 	TECHNOLOGY_L1_HW_PREFETCH,
 	TECHNOLOGY_L1_HW_IP_PREFETCH,
-	TECHNOLOGY_L1_NLP_PREFETCH,
+	TECHNOLOGY_L1_NPP_PREFETCH,
 	TECHNOLOGY_L1_SCRUBBING,
 	TECHNOLOGY_L2_HW_PREFETCH,
 	TECHNOLOGY_L2_HW_CL_PREFETCH,

x86_64/intel_reg.h

@@ -439,6 +439,7 @@
 #define MSR_ATOM_L2_PREFETCH_0X1321		0x00001321
 #define MSR_ATOM_L2_PREFETCH_0X1322		0x00001322
 #define MSR_ATOM_L2_PREFETCH_0X1323		0x00001323
+#define MSR_ATOM_L2_PREFETCH_0X1324		0x00001324
 
 typedef union
 {
@@ -766,7 +767,7 @@ typedef union
 		L2_HW_CL_Prefetch	:  2-1,  /* NHM, SNB		*/
 		L1_HW_Prefetch		:  3-2,  /* Avoton, Goldmont, NHM, SNB*/
 		L1_HW_IP_Prefetch	:  4-3,  /* NHM, SNB		*/
-		L1_NLP_Prefetch		:  5-4,  /* DCU Next Page Prefetcher */
+		L1_NPP_Prefetch		:  5-4,  /* DCU Next Page Prefetcher */
 		L2_AMP_Prefetch 	:  6-5,  /* 12th, 13th Gen; Xeon 4th */
 		ReservedBits2		: 11-6,
 		DISABLE_THREE_STRIKE_CNT: 12-11, /* Errata [ADL021]	*/
@@ -859,6 +860,17 @@ typedef union
 	};
 } ATOM_L2_PREFETCH_0X1323;
 
+typedef union
+{	/* MSR_ATOM_L2_PREFETCH(0x00001324): Atom E-Core only		*/
+		unsigned long long	value;
+	struct {
+		unsigned long long
+		pad0				: 54-0,
+		L1_HOMELESS_THRESHOLD		: 62-54,
+		pad1				: 64-62;
+	};
+} ATOM_L2_PREFETCH_0X1324;
+
 typedef union
 {
 	unsigned long long	value;