Topology

[cyring]

• Hyperthreading state through Proc->Features.HTT_enabled=1 can be set during the final loop. Right after kthread_stop()
• Disabled cpus by Kernel should be accounted by the topology algorithm. It appears that a core deactivation from Linux or from the BIOS differs , isn't ?

[cyring]

Fixed

[cyring]

[AMD] Introducing the Core Complex ID.

Remarks:

1. Executed in a virtualized QEMU/Epyc processor for the topology testing purpose.
   Thus some data are not relevant, such as the BCLK.
2. The blue CPUs have been voluntary disabled.
3. QEMU does not virtualize SMT, thus no Thread ID detected.
   Two bare metal runs, respectively SMT ON then OFF in BIOS will complete the CCX test. Your screenshot results are welcomed

[adatum]

As requested in #54 (comment) Very cool to be seeing CCX info!

SMT OFF

SMT ON

[cyring]

As requested in #54 (comment) Very cool to be seeing CCX info!

You're welcome. Glad to see it works.

Hope others will push TR and Epyc results.

[logan2611]

Confirmed to work on Zen 2 👍

[cyring]

Confirmed to work on Zen 2

Super, thanks a lot.

Meanwhile I have to check why L3 Way equals 9 !

Edit: can you post the CPUID output of CPU number 0 using command corefreq-cli -u

[cyring]

For all AMD: the latest commit is fixing the number of L2 , L3 Cache Way Associativity.
Can you plz update and screenshot the topology again ?

[adatum]

[cyring]

@adatum : apparently it matches the cache specs

[cyring]

Should we divide the L3 cache size per CCX count ?

[cyring]

Should we divide the L3 cache size per CCX count ?

Nothing to see with CCX; in fact the CPUID_Fn80000006_EDX [L3 Cache Identifiers] in Zen PPR says about the L3 cache size that for any queried value in range FFFh-0001h, the size equals (<Value> *0.5) MB

[cyring]

L3 Size fix committed for your test

[adatum]

The Topology window now requires scrolling. Other than L3 the values are the same as before.

[cyring]

The Topology window now requires scrolling. Other than L3 the values are the same as before.

Changes happened in Daemon code not Cli. L3 cache size has been fixed.

1. Perhaps moving cursor around L3 column will reveal cell sizing issue ?
2. Immediately after opening the window, does the cursor still land onto cell 00: BSP 0 ?
3. Do you have the same behavior if using XTerm ?

[adatum]

1. Perhaps moving cursor around L3 column will reveal cell sizing issue ?

Do you mean to the right/left? The scrolling is only vertical, nothing out of the window horizontally.

2. Immediately after opening the window, does the cursor still land onto cell `00: BSP     0` ?

Yes the cursor defaults to that cell when the Topology window is opened.

3. Do you have the same behavior if using XTerm ?

Yes, same with XTerm:

[cyring]

The same if you resize the Terminal to a bigger dimension; like 100 lines ?

[adatum]

Yes, still same. The Topology window size does not change based on the terminal window size.

[cyring]

Transferred to the roadmap #169

[cyring]

Topology needs refactoring:

1. It's hard to read.
   Better show the sum for all Cores, especially in the UI header
   EDIT: Looking at code, it may be hazardous to compute the sum of L1 & sum of L2 in those cases:

• Hyperthreading enabled or not
• Count of virtualized processors
• Disabled Core(s) excluded from the sum

A straight forward answer would be:

TotalSize_L{1,2} = ( CPU_Count x PerCpu_L{1,2}_Size ) / ( 1 + HyperThreading_State[0,1] )

However this formula will wrong in a virtualized platform.

2. L3 size is wrong.
   The 512 multiplier seems not to be applied among Zen generations, among Ryzen vs Threadripper
   EDIT: Code is being fixed in the development branch.

[cyring]

L3 size checked with some AMD Zen processors