Raptor Lake, 13900k no bus or memory info #404
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Nice. This is the first received report about Globally CoreFreq support appears good. Especially the Hybrid topology. To complete with the IMC Memory Controller, I will need you post the output of I'm also observing a Target Ratio of Vcore is supplied for PCore but not computed yet with the Ecore yet, although we see a |
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lspci -nn |
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You can now try to decode the IMC from the latest |
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Looks good: |
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Do you have 4 sticks of 8GB DIMM ? |
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No, 2 16 GB Sticks.
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Do you have 4 sticks of 8GB DIMM ?
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Thing I did not notice with Alder Lake i9-12900K but later with AMD Zen3+ is the DDR5 in quad channels. Here 13900K has 2 x DDR5 DIMMs in quad channels mode (thing you may read in other Windows tools) but contrary to AMD, Intel seems to split each DIMM in 2 registers sets, same settings but half size. One for each 32 bits mode. This could be the trick they used to keep the registers specs the same as previous arch: Alder Lake. So facing DDR5, CoreFreq algorithm will have to sacrifice one every two controllers; let's say the odd identifiers and alter Geometry to reflect the true size. |
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Hello, Can you give a quick test to this version and post the Memory Controller output ? In case you have an Alder Lake, the same test will help for non regression. Thank you |
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Meanwhile I have completed the support list of Chipsets: can you pull the Thank you |
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Thank you.
Uncore range change is btw available in branch. |
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Does your BIOS say "Dual" or "Quad" channels ? |
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From manual, Memory Channels Timing screens are those I would like to see, plz. |
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Another request is to change the Voltage scope to [Core] or [SMT] and see if Vcore gets resolved for both Pcore and Ecore ? |
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Here are all setting screens I could find + cpu-z output:
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Set to Core: |
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Thank you. So CPU-Z is showing it as Quad 32-bits channels, like for Zen, but Intel differs from AMD in the number of controllers associated: for two DIMM sticks, 2 controllers for Intel vs 4 controllers for AMD Somehow CoreFreq does not report |
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Hello, Using latest commits, you will get:
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Can you also switch to Experimental mode in Next you set for example a |
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REFI is now broken max value is 262143 I use 111111: Duty Cycle 50%: |
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Small correction to the duty cycle is applied, just not displayed correctly. |
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Thank you for your answers I will thus make I wonder if Could you also refresh from I am interested by the IMC timings part like it has been tested on Alder Lake: |
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Yes !
But not on ADL + DDR4 |
Space is indeed missing: only 5 digits. |
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You can now pull the last commit to read Available for Intel DDR4/DDR5 |
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Yes, everything is working. Thank you for your help. Is the possibility to set memory timings planed? |
I would jump on such feature if allowed to do it but datasheets I have read so far say no, read-only.
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Could you try this view again (using the very last commit) to see if the SA (System Agent) VID is now converting into voltage ? |
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If you look at my BIOS screenshots, there is a setting "Realtime Memory Timing" This allows to write access, but I don't know if it uses the same registers. |
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SA voltage is the Voltage which is set in BIOS. |
And I wonder if it talks about SPD data as mentioned here : I have no clue of such Registers. Do you know if XTU or other low-level Windows software are capable to alter IMC timings ? Concerning the IMC Registers I'm using in CoreFreq: in the past I have forced writing them through MMIO mapping and it immediately crashed kernel. |
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Allok |
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Hello, I forgot to activate the Uncore PMU Can you please pull and build from latest The |
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Small addition, the min value doesn't get applied. I have to check if this maybe is BIOS related, uncore always moves around 4.2Ghz - 4.5Ghz |
Very odd because you have a K processor. I have been able to alter Min ratio from a Mobile Tiger Lake |
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This MSR Line 146 in b703886 This bits specification Line 1509 in b703886 Presuming ## Read initial ratios
rdmsr -ax 0x000006200x0832
...
0x0832## Write Min ratio to 0x32
wrmsr -a 0x00000620 0x3232
## Read register again to check if value is taken into account
rdmsr -ax 0x000006200x3232 ## is OK |
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I tested a bit further as long as the E-Cores are not loaded the min/max get applied if all cores are loaded the BIOS seems to have a hard-coded limit of 4,5Ghz. I can override this in the BIOS, but its pointless performance doesn't increase, but power usage does. |
Thank you for your return. |
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Hello, Using latest Since your last test, developments have impacted the Bus Rate and Speed, DRAM Speed, Controllers topology. |
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Thank you for your IMC data. It looks coherent with what I can google about |
corefreq-cli -s -n -m -n -B -n -M -n -C 1
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