Veryl is a modern hardware description language.
This project is under the exploration phase of language design. We call for the following suggestion or contribution:
- Language design
- Tool implementation
- Standard library implementation
If you have any idea, please open Issue or Pull request.
Veryl is a hardware description language based on SystemVerilog, providing the following advantages:
Veryl adopts syntax optimized for logic design while being based on a familiar basic syntax for SystemVerilog experts. This optimization includes guarantees for synthesizability, ensuring consistency between simulation results, and providing numerous syntax simplifications for common idioms. This approach enables ease of learning, improves the reliability and efficiency of the design process, and facilitates ease of code writing.
Designed with interoperability with SystemVerilog in mind, Veryl allows smooth integration and partial replacement with existing SystemVerilog components and projects. Furthermore, SystemVerilog source code transpiled from Veryl retains high readability, enabling seamless integration and debugging.
Veryl comes with a rich set of development support tools, including package managers, build tools, real-time checkers compatible with major editors such as VSCode, Vim, Emacs, automatic completion, and automatic formatting. These tools accelerate the development process and significantly enhance productivity.
With these features, Veryl provides powerful support for designers to efficiently and productively conduct high-quality hardware design.
| Veryl | SystemVerilog |
|---|---|
/// documentation comment by markdown format
/// * list item1
/// * list item2
pub module Delay #( // visibility control by `pub` keyword
param WIDTH: u32 = 1, // trailing comma is allowed
) (
i_clk : input clock ,
i_rst : input reset ,
i_data: input logic<WIDTH>,
o_data: output logic<WIDTH>,
) {
// unused variable which is not started with `_` are warned
var _unused_variable: logic;
// clock and reset signals can be omitted
// because Veryl can infer these signals
always_ff {
// abstraction syntax of reset polarity and synchronicity
if_reset {
o_data = '0;
} else {
o_data = i_data;
}
}
} |
// comment
//
//
module Delay #(
parameter int WIDTH = 1
) (
input i_clk ,
input i_rst ,
input [WIDTH-1:0] i_data,
output [WIDTH-1:0] o_data
);
logic unused_variable;
always_ff @ (posedge i_clk or negedge i_rst) begin
if (!i_rst) begin
o_data <= '0;
end else begin
o_data <= i_data;
end
end
endmodule |
SystemVerilog is very complicated language, and it causes difficulty of implementing EDA tools for it. As a consequence, major EDA tools only support SystemVerilog subset which is different each other, and users must explore usable languege features which are covered by adopted tools. Additionally, the difficulty prevents productivity improvement by developing support tools. This is a reason that a new language having simplified and sophisticated syntax, not SystemVerilog, is required.
Many existing alt-HDLs are inner DSL of a programming language.
This approach has some advantages like rapid development and resusable tooling ecosystem,
but the syntax can't be fit for hardware description completely.
Additionally, enormous Verilog code is generated from short and sophisticated code in these languages.
This prevents general ASIC workflows like timing improvement, pre/post-mask ECO because these workflows require FF-level modification in Verilog.
Interopration between these language and SystemVerilog is challenging because these can't connect to SystemVerilog's type like interface and struct directly.
By these reason, the existing Alt-HDLs can't be used as alternative of SystemVerilog, especially if there are many existing SystemVerilog codebase.
Veryl resolves these problems by HDL-specialized syntax and human-readable SystemVerilog code generation.
Veryl focuses equivalency with SystemVerilog at the point of view of the language semantics. This eases to predict the changes of generated SystemVerilog code from modification of Veryl code, and Veryl can be applied to ASIC workflows like timing improvement and pre/post-mask ECO. Therefore, some features generating FFs are not adopted because these prevent the predictability.
Veryl focuses syntax simplicity because it reduces tool implementation effort. Therefore syntax features which introduce large complexity in exchange for slight abbreviation are not adopted.
See Getting Started.
Licensed under either of
- Apache License, Version 2.0, (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
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