v0.6.3

Patch Changes

• 14b2a07: A 74HC595 with SRCLK and RCLK wired together now runs its outputs one clock behind its shift register, as the real chip does. With the clocks tied, one rising edge clocks both registers, and the storage register samples the shift register before that edge's shift reaches it. TI's data sheet (SN74HC595, SCLS041J, section 8.1) says that with both clocks connected together "the shift register always is one clock pulse ahead of the storage register." The model stored the bit the edge had just shifted in, so the outputs ran one clock ahead of a real board: with the model's storage register starting empty, the first clock after load lit QA when SER was high, and now the outputs stay dark until the second clock. The two tied pins are now read as one input, so a slow edge that sits between the input thresholds for a step (an RC-debounced button, say) clocks both registers in the same step instead of shifting first and latching later. A /SRCLR clear seen in the same step as a tied edge still stores zeros, as it does with separate clocks. SRCLK and RCLK on separate nets are unchanged, including when both rise in one step: a latch pulse just after the last shift stores the shifted byte, as it does on hardware.

• 4878620: A ferrite bead can now fail from overload. Its catalog entry carries a power rating (p_max) that the engine never read, so a bead carried any current for as long as the circuit ran: 10 A through the old 0.5 ohm default, 50 W against a 0.25 W rating, never failed it. A bead now dissipates its current squared times the resistance it conducts with (rDc; the catalog's 3.5 mohm for a bead that has none, and never below 1 mohm) and is rated like a resistor: above p_max the damage grows by (power / p_max - 1) per second, it bleeds off at 1 per second inside the rating, and the bead fails open when it reaches 1. A bead dissipating 1.2 times its power rating therefore lasts 5 s. The failure is the existing resistor_overload with the resistor's message, so a host that reports a failed resistor reports a failed bead without a change. A failed bead is open in the transient, operating-point and small-signal analyses until resetFailures(). A bead with its own rDc inside its rating is unchanged, and a p_max of 0 or less, or none, still means no limit. Only the DC resistance is rated: the model has no frequency-dependent impedance, so it has no high-frequency heating.

  The catalog's bead data is corrected as well. The default DC resistance, the catalog's and the engine's for a bead with no rDc, was 0.5 ohm and is now 3.5 mohm, the resistance of the 22 AWG lead on the Fair-Rite 2743001111 the part is modelled on, so a default bead in series now drops about 1/143 of the voltage it did. Fair-Rite controls this bead for impedance only and gives it no current rating, so the catalog's 2 A is its own assumption, unverified, and p_max is now 0.056 W, the power at twice that current ((2 x 2 A)^2 x 3.5 mohm). A bead at 2 A never fails and the default bead fails above 4 A DC: 5 A (1.56 times the power rating) takes 1.8 s and 10 A takes 0.19 s. A bead saved with its own rDc, the old 0.5 ohm for one, keeps it and gets the same 0.056 W rating, so it fails above about 0.335 A.

• 685179c: HeadlessRunner no longer steps over a source's edges and short pulses. It limited its step size by each source's frequency but did not choose where steps fall, and the engine reads a source at the end of each step, so a step that crossed an edge applied the new level for the whole step, and a feature shorter than a step could be missed entirely. A PWL source has no step limit, so a 0.2 ms pulse at 3 ms never showed in a 20 ms run (22 steps, up to 8.2 ms each), and neither did the 21 us pulse of a one-shot pulse_source (per 0). A 20 us pulse every 1 ms, from a signal_gen or a pulse_gen, showed only in the first period: 11.2 us HIGH over 20 ms instead of 420 us. The runner now places steps the way de:volt's browser simulator does. It lands a step 10 ns before each source event (every edge and corner of a clock, clock_gen, pulse_source, pulse_gen or signal_gen, every PWL point, every 0.1 ms noise sample, and the start of a delayed waveform), then crosses the event in a 10 ns step. Pulses down to about 10 ns wide now show (the 20 us pulse reads 419.6 us HIGH), and a new level arrives at most 15 ns early. Landing on an event costs up to two extra steps (a 1 kHz square or clock into a resistor takes 254 steps over 20 ms instead of 214, a noise generator 613 instead of 413), and a circuit that now sees pulses it used to miss takes the steps its response needs: a 1 kohm, 100 nF RC fed the 20 us pulses takes 2043 instead of 489. Fixed-step runs (adaptive: false) take the same short steps at each event, so their samples are no longer evenly spaced around one: a 1 kHz clock at 10 us steps takes a 9.99 us and a 10 ns step at each edge. A circuit with none of these sources steps exactly as before, as does a sine, triangle or DC signal_gen that starts at t = 0.

• a1413c1: A logic output that drives only capacitors no longer reports a false output_sag on its edges. The check confirmed a sag one solve after the output switched, and the simulation's step lags a fast RC edge there: a 74LS04 driving 30 pF is back inside its LOW band 8.6 ns after a falling edge, but a 10 ns step still left the pin at 1.6 V against the 0.8 V limit, so every falling edge raised a sag; driving 100 pF, every rising edge did the same whenever the step was 10 ns. Where the output's net is provably a single RC stage, a sag now counts only if an upper bound of how long it really lasts reaches 10 ns. The bound comes from the output resistance, the capacitance and the capacitor's ESR and leakage, and it starts from the farthest point the edge could have begun at: the capacitor's own state when the solve that first sees the sag began, or the farthest rail or far end. That covers capacitors placed from the catalog with their default ESR and leakage, outputs switched on by an enable, and capacitors still charged from before a reload. A net is a single stage when a 74-series, CD4017, CD4511, CD4060 or 28C-memory output, on supplies from ideal voltage sources, drives nothing but other logic inputs and either one capacitor or several without ESR, each returned to ground, a supply or another fixed voltage, and the simulation uses backward Euler, its default. Every other output keeps the old two-step check, since a series resistor, a pull-up, a second driver or a second capacitor with ESR can make an edge last longer than the bound assumes; a sag shorter than 10 ns can still be reported there, as before. Any sag the bound does not rule out is judged by the old check exactly as before. A sag that ends within a single simulation step is still not seen. One case is not covered: a direct caller that changes a source voltage, or a capacitor's ESR or leakage, between steps without load() while a sag is already under way, where that change is what stretches the sag past 10 ns.

• 8024715: Switching off a 555 blinker's power no longer freezes the simulation. On a 9 V battery, opening a power switch in either battery lead, or pulling the chip's ground wire, while the timing capacitor held more than about 4 V stalled it: the status showed SETTLING with fail=1/1 and the clock stood still until the power came back. That capacitor and the two timing resistors were all that still fed the 555, and they could not carry its supply current. Switched on, the chip pulled its own supply below its 4 V turn-on threshold and starved itself; switched off, the capacitor lifted the supply back above the threshold, and the solver never settled between the two. HeadlessRunner met the same dead end when a 555 ran on a decoupling capacitor after its rail's bridge to the battery was removed, and stopped about 17 ms later as the capacitor drained through the threshold. Now, when a step fails while a chip's power flips like that, the engine checks, with every capacitor holding its present charge, whether the chip could keep its supply switched on and whether the supply comes back with the chip switched off. A chip that starves itself that way counts as off for that step, and the clock keeps running. A chip whose supply is still rising through its turn-on threshold is not starving itself: that step is rejected exactly as before, so the shorter step that follows turns the chip on at the same moment as before. The exception is a step already at the 10 ns minimum step size, where no shorter step is left: there the chip is held off for that one 10 ns step instead of the clock stopping, and turns on as soon as its supply can carry it. Run in 0.5 ms pieces, HeadlessRunner used to stop 6 ms into powering up a 74LS04 from a 9 V battery through 100 Ω onto a 100 µF rail; it now runs on, and the chip lights its LEDs about 12 µs after its rail reaches the threshold. A step the check cannot settle is rejected exactly as before too, so a smaller step can still find the answer, and circuits that never hit this case are bit-identical. This covers the same chips as the unconnected-rail fix: the 555, 74xx and CD4000 logic, the 28C16 and 28C256 EEPROMs, the HD44780 and MAX7219 displays and the LM393.

• 5657a9a: A signal_gen whose waveform is not one of the eight names the engine knows now gets a sine's step limit in HeadlessRunner. The engine plays any other value as a sine ("Sine", "SQUARE", a typo, a number), but the runner picked the step limit from the raw string, so those sines got none: "Sine" at 1 kHz ran 22 steps over 20 ms, up to 8.2 ms each, and read above mid-scale for 1.1 ms instead of 10 ms. The runner now reads the waveform through the engine's own parse (parseSignalGenParams), so such a generator steps exactly like "sine": 812 steps, 25 us at most. The eight recognised names step exactly as before.