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Description
Hi Developers,
I'm trying to verify this 1011 sequence detector. Problem is the delay is not as expected, when I set a bigger delay such as 6 cycles and add reset before the sequence it gets proven, but that's incorrect. It's not getting proven for the 2 cycles delay without adding reset before the sequence.
Command used:
ebmc seq_detector_overlapping_ebmc.sv --top seq_detector_overlapping --bound 500 --reset reset==1 --vcd ebmc_counter.vcd
Code:
module seq_detector_overlapping(
input seq_in, clk, reset,
output logic detect_out
);
//one-hot encoding of FSM
enum logic [4:0] {S0 = 5'b00001, S1 = 5'b00010, S2 = 5'b00100, S3 = 5'b01000, S4 = 5'b10000} state, next;
//state registers
always_ff @(posedge clk or posedge reset)
if (reset) state <= S0;
else state <= next;
// Next state assignment logic
always_comb begin
next = state;
unique case (state)
S0 : if (seq_in) next = S1; else next = S0;
S1 : if (seq_in) next = S1; else next = S2;
S2 : if (seq_in) next = S3; else next = S0;
S3 : if (seq_in) next = S4; else next = S2;
S4 : next = S0;
endcase
end
// Registered output logic
always_ff @(posedge clk, posedge reset)
if (reset) detect_out <= 1'b0;
else detect_out <= (state == S4);
ASSUME_VALID_STATE: assume property ($onehot(state) and (reset |-> (state == S0)));
ASSERT_CHK_SEQ_DETECT: assert property (@(posedge clk) reset ##1 seq_in ##1 !seq_in ##1 seq_in ##1 seq_in |-> ##6 detect_out);
ASSERT_BI: assert property ( @(posedge clk) detect_out |-> (($past(seq_in, 2) == 1) && ($past(seq_in, 3) == 1) && ($past(seq_in, 4) == 0) && ($past(seq_in, 5) == 1)) );
endmodule
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