SystemVerilog: unbased unsized literals #1022
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kroening
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tautschnig
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Mar 17, 2025
src/verilog/convert_literals.cpp
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| if(rest == "'0") | ||
| { | ||
| return from_integer(0, unsignedbv_typet{1}); | ||
| } | ||
| else if(rest == "'1") | ||
| { | ||
| return from_integer(0, unsignedbv_typet{1}); | ||
| } |
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Should this be if(rest == "'0" || rest == "'1") to make clear there is no copy&paste mistake here?
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It is a copy/paste error; extended the test.
This adds the SystemVerilog unbased unsized literals.
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This adds the SystemVerilog unbased unsized literals.