fix for no-op assignments during Verilog synthesis #1103
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Assignments during Verilog synthesis may be no-op (e.g., out-of-bound). This fix prevents generating an untyped auxiliary variable assignment in this case. Fixes #1050.
tautschnig
approved these changes
May 8, 2025
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Assignments during Verilog synthesis may be no-op (e.g., out-of-bound). This fix prevents generating an untyped auxiliary variable assignment in this case.
Fixes #1050.