Verilog: module port declarations with default value #1258
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kroening
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This replaces the use of exprt in verilog_synthesist::instantiate_ports by a stronger type.
kroening
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This fixes the grammar to allow ANSI module port declarations that have a default value. This adds support for module ports (ANSI and non-ANSI) that have a default value to the type checker.
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tautschnig
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Sep 8, 2025
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This fixes the grammar to allow ANSI module port declarations that have a default value.
This adds support for module ports (ANSI and non-ANSI) that have a default value to the type checker.