Verilog: KNOWNBUG test for 1800-2017 10.10 unpacked array concatenation

regression/verilog/arrays/unpacked_array_concatenation1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+unpacked_array_concatenation1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This yields a type checking error.

regression/verilog/arrays/unpacked_array_concatenation1.sv

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+module main;
+
+  // 1800-2017 10.10 Unpacked array concatenation
+  byte my_bytes [1:4] = { 1, 2, 3, 4 };
+
+  assert final(my_bytes[1] == 1);
+  assert final(my_bytes[2] == 2);
+  assert final(my_bytes[3] == 3);
+  assert final(my_bytes[4] == 4);
+
+endmodule