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Verilog: KNOWNBUG test for config #1310

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Merged
merged 1 commit into from
Oct 10, 2025
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Verilog: KNOWNBUG test for config #1310

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9 changes: 9 additions & 0 deletions regression/verilog/config/basic_config1.desc
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Original file line number Diff line number Diff line change
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KNOWNBUG
basic_config1.sv
--module top
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This does not parse.
13 changes: 13 additions & 0 deletions regression/verilog/config/basic_config1.sv
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module SUB;
parameter P = 1;
endmodule

module top;
SUB sub();
endmodule

config some_config;
design top;
instance top.sub use #(.P(2));
endconfig

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