Verilog: move grammar rules into correct section #297
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This moves statement-related rules into the right section, and adjusts initial/always rules to match the System Verilog standard.
tautschnig
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Dec 15, 2023
Romy15200
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Aug 19, 2025
Verilog: move grammar rules into correct section
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This moves statement-related rules into the right section, and adjusts initial/always rules to match the System Verilog standard.