Verilog: assignment pattern expressions #578
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kroening
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tautschnig
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| if(dest_type.id() == ID_struct) | ||
| { | ||
| auto &struct_type = to_struct_type(dest_type); | ||
| auto &components = struct_type.components(); | ||
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| if(expr.operands().size() != components.size()) | ||
| { | ||
| throw errort().with_location(expr.source_location()) | ||
| << "number of expressions does not match number of struct members"; | ||
| } | ||
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| for(std::size_t i = 0; i < components.size(); i++) | ||
| { | ||
| // rec. call | ||
| implicit_typecast(expr.operands()[i], components[i].type()); | ||
| } | ||
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| // turn into struct expression | ||
| expr.id(ID_struct); | ||
| expr.type() = dest_type; | ||
| return; | ||
| } |
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The earlier comment said these could become structs or arrays -- are the latter just not yet implemented?
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Array case added.
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This adds support for struct and array literals to the SystemVerilog frontend by implementing the assignment_pattern_expression production rules.
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Verilog: assignment pattern expressions
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This adds support for struct and array literals to the SystemVerilog frontend by implementing the
assignment_pattern_expressionproduction rules.