SystemVerilog: named properties #579
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Concurrent assertion items (assert/assume/cover) that are module items with a block label go into the module name space, not into a separate "property" name space. Assertion items without block item now get a label based on the kind of the assertion item (assert/assume/cover).
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This adds support for SystemVerilog named properties.
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tautschnig
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Jun 25, 2024
| CORE | ||
| named_property1.sv | ||
| --bound 0 | ||
| ^\[main\.assert\.1\] always main\.x == 10: PROVED up to bound 0$ |
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Wouldn't it make sense for x_is_ten to be used here in some way?
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I'd like that -- it would require splitting up the type checking phase such that the initial phase doesn't expand symbols marked as "macro". Will do eventually.
tautschnig
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Jun 28, 2024
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SystemVerilog: named properties
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This adds support for SystemVerilog named properties.